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2019-10-13ARM: dts: rockchip: Add RK3288 VOP gamma LUT addressEzequiel Garcia1-2/+2
RK3288 SoC VOPs have optional support Gamma LUT setting, which requires specifying the Gamma LUT address in the devicetree. Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20191010194351.17940-4-ezequiel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-30ARM: dts: rockchip: Add cpu id to rk3288 efuse nodeDouglas Anderson1-0/+3
This just adds in another field of what's stored in the e-fuse on rk3288. Though I can't personally promise that every rk3288 out there has the CPU ID stored in the eFuse at this location, there is some evidence that it is correct: - This matches what was in the Chrome OS 3.14 branch (see EFUSE_CHIP_UID_OFFSET and EFUSE_CHIP_UID_LEN) for rk3288. - The upstream rk3399 dts file has this same data at the same offset and with the same length, indiciating that this is likely common for several modern Rockchip SoCs. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20190919142611.1.I309434f00a2a9be71e4437991fe08abc12f06e2e@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-06ARM: dts: rockchip: Add unwedge pinctrl entries for dw_hdmi on rk3288Douglas Anderson1-0/+9
This adds the "unwedge" pinctrl entries introduced by a recent dw_hdmi change that can unwedge the dw_hdmi i2c bus in some cases. It's expected that any boards using this would add: pinctrl-names = "default", "unwedge"; pinctrl-0 = <&hdmi_ddc>; pinctrl-1 = <&hdmi_ddc_unwedge>; Note that this isn't added by default because some boards may choose to mux i2c5 for their DDC bus (if that is more tested for them). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-04ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3John Keeping1-1/+1
This is the same as the other PWMs on this SoC and uses 3 cells. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-05-22ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288Matthias Kaehlcke1-4/+0
The NPLL is the only safe way to generate 500 MHz for the GPU. The downstream Chrome OS 3.14 kernel ('official' kernel for veyron devices) re-purposes NPLL to HDMI and hence disables the OPP for the GPU (see https://crrev.com/c/1574579). Disable it here as well to keep in sync and avoid problems in case someone decides to re-purpose NPLL. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> [moved from veyron to general rk3288, as tying up the NPLL for a not-that-helpful opp (not really fast but will still generate quite a bit of heat) doesn't make so much sense when it will keep us from supporting other display modes in the future] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-05-22ARM: dts: rockchip: Use GPU as cooling device for the GPU thermal zone of the rk3288Matthias Kaehlcke1-4/+1
Currently the CPUs are used as cooling devices of the rk3288 GPU thermal zone. The CPUs are also configured as cooling devices in the CPU thermal zone, which indirectly helps with cooling the GPU thermal zone, since the CPU and GPU temperatures are correlated on the rk3288. Configure the ARM Mali Midgard GPU as cooling device for the GPU thermal zone instead of the CPUs. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-05-22ARM: dts: rockchip: Add #cooling-cells entry for rk3288 GPUMatthias Kaehlcke1-0/+1
The Mali GPU of the rk3288 can be used as cooling device, add a #cooling-cells entry for it. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-05-22ARM: dts: rockchip: Mark that the rk3288 timer might stop in suspendDouglas Anderson1-0/+1
This is similar to commit e6186820a745 ("arm64: dts: rockchip: Arch counter doesn't tick in system suspend"). Specifically on the rk3288 it can be seen that the timer stops ticking in suspend if we end up running through the "osc_disable" path in rk3288_slp_mode_set(). In that path the 24 MHz clock will turn off and the timer stops. To test this, I ran this on a Chrome OS filesystem: before=$(date); \ suspend_stress_test -c1 --suspend_min=30 --suspend_max=31; \ echo ${before}; date ...and I found that unless I plug in a device that requests USB wakeup to be active that the two calls to "date" would show that fewer than 30 seconds passed. NOTE: deep suspend (where the 24 MHz clock gets disabled) isn't supported yet on upstream Linux so this was tested on a downstream kernel. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-05-20ARM: dts: rockchip: fix PWM clock found on RK3288 SocsCaesar Wang1-4/+4
We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect. Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-05-16Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-156/+161
Pull ARM Device-tree updates from Olof Johansson: "Besides new bindings and additional descriptions of hardware blocks for various SoCs and boards, the main new contents here is: SoCs: - Intel Agilex (SoCFPGA) - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus) New boards: - Allwinner: + RerVision H3-DVK (H3) + Oceanic 5205 5inMFD (H6) + Beelink GS2 (H6) + Orange Pi 3 (H6) - Rockchip: + Orange Pi RK3399 + Nanopi NEO4 + Veyron-Mighty Chromebook variant - Amlogic: + SEI Robotics SEI510 - ST Micro: + stm32mp157a discovery1 + stm32mp157c discovery2 - NXP: + Eckelmann ci4x10 (i.MX6DL) + i.MX8MM EVK (i.MX8MM) + ZII i.MX7 RPU2 (i.MX7) + ZII SPB4 (VF610) + Zii Ultra (i.MX8M) + TQ TQMa7S (i.MX7Solo) + TQ TQMa7D (i.MX7Dual) + Kobo Aura (i.MX50) + Menlosystems M53 (i.MX53)j - Nvidia: + Jetson Nano (Tegra T210)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits) arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge arm64: dts: bitmain: Add pinctrl support for BM1880 SoC arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board arm64: dts: bitmain: Add GPIO support for BM1880 SoC ARM: dts: gemini: Indent DIR-685 partition table dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20 arm64: dts: msm8998: thermal: Fix number of supported sensors arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones arm64: dts: exynos: Move fixed-clocks out of soc arm64: dts: exynos: Move pmu and timer nodes out of soc ARM: dts: s5pv210: Fix camera clock provider on Goni board ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210 ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250 ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250 ARM: dts: exynos: Move pmu and timer nodes out of soc arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64 arm64: dts: db820c: Add sound card support arm64: dts: apq8096-db820c: Add HDMI display support ...
2019-05-03ARM: dts: rockchip: Add quirk for resetting rk3288's dwc2 host on wakeupDouglas Anderson1-0/+1
The "host" USB port on rk3288 has a hardware errata where we've got to assert a PHY reset whenever we see a remote wakeup. Add that quirk property to the device tree. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2019-05-03ARM: dts: rockchip: Hook resets up to USB PHYs on rk3288.Douglas Anderson1-0/+6
Let's hook up the resets to the three USB PHYs on rk3288 as per the bindings. This is in preparation for a future patch that will set the "snps,reset-phy-on-wake" on the host port. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2019-04-12ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288Matthias Kaehlcke1-0/+4
The value was determined with the following method: - take CPUs 1-3 offline - for each OPP - set cpufreq min and max freq to OPP freq - start dhrystone benchmark - measure CPU power consumption during 10s - calculate Cx for OPPx - Cx = (Px - P1) / (Vx²fx - V1²f1) [1] using the following units: mW / Ghz / V [2] - C = avg(C2, ..., Cn) [1] see commit 4daa001a1773 ("arm64: dts: juno: Add cpu dynamic-power-coefficient information") [2] https://patchwork.kernel.org/patch/10493615/#22158551 FTR, these are the values for the different OPPs: freq (kHz) mV Px (mW) Cx 126000 900 39 216000 900 66 370 312000 900 95 372 408000 900 122 363 600000 900 177 359 696000 950 230 363 816000 1000 297 361 1008000 1050 404 362 1200000 1100 528 362 1416000 1200 770 377 1512000 1300 984 385 1608000 1350 1156 394 Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11ARM: dts: rockchip: bulk convert gpios to their constant counterpartsHeiko Stuebner1-143/+143
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-25ARM: dts: rockchip: Remove #address/#size-cells from rk3288 mipi_dsiDouglas Anderson1-2/+0
They are pointless. As dtc points out: Warning (avoid_unnecessary_addr_size): /mipi@ff960000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Let's remove them. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-25ARM: dts: rockchip: Fix gpu opp node names for rk3288Douglas Anderson1-6/+6
The device tree compiler yells like this: Warning (unit_address_vs_reg): /gpu-opp-table/opp@100000000: node has a unit name, but no reg property Let's match the cpu opp node names and use a dash. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-21ARM: dts: rockchip: Fix gic/efuse sort ordering for rk3288Douglas Anderson1-13/+13
It can be seen that 0xffb40000 < 0xffc01000, thus efuse comes first. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-18ARM: dts: rockchip: add grf reference in rk3288 tsadc nodeJonas Karlman1-0/+1
The following message can be seen during boot: rockchip-thermal ff280000.tsadc: Missing rockchip,grf property Fix this by adding rockchip,grf property to tsadc node. The warning itself is not relevant on rk3288 right now, as the tsadc doesn't need to set GRF-values at this point and only newer variants do. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-18ARM: dts: rockchip: fix rk3288 cpu opp node referenceJonas Karlman1-3/+3
The following error can be seen during boot: of: /cpus/cpu@501: Couldn't find opp node Change cpu nodes to use operating-points-v2 in order to fix this. Fixes: ce76de984649 ("ARM: dts: rockchip: convert rk3288 to operating-points-v2") Cc: stable@vger.kernel.org Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-12-06ARM: dts: rockchip: add VPU device node for RK3288Ezequiel Garcia1-1/+13
Add the Video Processing Unit node for RK3288 SoC. Fix the VPU IOMMU node, which was disabled and lacking its power domain property. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-19ARM: dts: rockchip: Add all CPUs in cooling mapsViresh Kumar1-3/+12
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-06-18ARM: dts: rockchip: Add missing cooling device properties for CPUs on rk3288Viresh Kumar1-0/+12
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> [follow conversion to operating-points-v2] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-06-18ARM: dts: rockchip: convert rk3288 to operating-points-v2Heiko Stuebner1-15/+55
Operating points need to be present in each cpu core using it, not only the first one. With operating-points-v1 this would require duplicating this table into each cpu node. With opp-v2 we can share the same table on all nodes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2018-06-17ARM: dts: rockchip: use SPDX-License-IdentifierKlaus Goger1-39/+1
Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers. All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only) claim to be GPL and X11 while the actual license text is MIT. Use the MIT SPDX tag for them. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Brian Norris <briannorris@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-04-16ARM: dts: rockchip: add clocks in iommu nodesJeffy Chen1-0/+12
Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-04-16ARM: dts: rockchip: fix uart4 pin-numbers for rk3288Jacob Chen1-4/+4
According to TRM, uart4 tx/rx should be 14/15 Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-03-05ARM: dts: rockchip: Add missing #sound-dai-cells on rk3288Rob Herring1-0/+2
dtc now gives the following warning: arch/arm/boot/dts/rk3288-tinker.dtb: Warning (sound_dai_property): /sound/simple-audio-card,codec: Missing property '#sound-dai-cells' in node /hdmi@ff980000 or bad phandle (referred from sound-dai[0]) Add the missing #sound-dai-cells property. Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-12-04ARM: dts: rockchip: fix rk3288 iep-IOMMU interrupts property cellsRob Herring1-1/+1
The interrupts property in the iep-IOMMU node for the rk3288 dts file has a spurious extra cell causing a dtc warning: Warning (interrupts_property): interrupts size is (16), expected multiple of 12 in /iommu@ff900800 Remove the extra cell. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-10-21ARM: dts: rockchip: define the two possible rk3288 CEC pinsHans Verkuil1-0/+8
The CEC line can be routed to two possible pins. Define those pins. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-10-21ARM: dts: rockchip: add the cec clk for dw-hdmi on rk3288Hans Verkuil1-2/+2
The dw-hdmi block needs the cec clk for the rk3288. Add it. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-10-17ARM: dts: rockchip: add RGA device node for RK3288Jacob Chen1-0/+11
This patch add the RGA dt config of rk3288 SoC. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17ARM: dts: rockchip: add LVDS node for rk3288Sandy Huang1-0/+52
Add LVDS info in rk3288.dtsi for LVDS driver Signed-off-by: Sandy Huang <hjc@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-24Merge tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dtArnd Bergmann1-89/+126
Pull "second round of Rockchip dts32 changes for 4.14" from Heiko Stübner: A lot of attention for the rv1108 soc targetted at media-processing (usb, operating points, spi, pwm, adc, watchdog, i2c and devices for its evb). RK3228/3229 gets iommu and spi nodes. Similar to the rk3288 which also gets some more iommu nodes as well as getting converted to 64 bit addresses due to wanting to address more than 4GB of memory via LPAE. * tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: enable usb for rv1108-evb ARM: dts: rockchip: add usb nodes for rv1108 SoCs dt-bindings: update grf-binding for rv1108 SoCs ARM: dts: rockchip: add cpu power supply for rv1108 evb ARM: dts: rockchip: add cpu opp table for rv1108 ARM: dts: rockchip: add rk322x iommu nodes ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb ARM: dts: rockchip: add pwm backlight for rv1108 evb ARM: dts: rockchip: add pwm dt nodes for rv1108 ARM: dts: rockchip: add spi dt node for rv1108 ARM: dts: rockchip: add saradc support for rv1108 ARM: dts: rockchip: add watchdog dt node for rv1108 ARM: dts: rockchip: add i2c dt nodes for rv1108 clk: rockchip: fix up indentation of some RV1108 clock-ids clk: rockchip: rename the clk id for HCLK_I2S1_2CH clk: rockchip: add more clk ids for rv1108 ARM: dts: rockchip: add more iommu nodes on rk3288 ARM: dts: rockchip: convert rk3288 device tree files to 64 bits ARM: dts: rockchip: add spi node and spi pinctrl on rk3228/rk3229 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-08-06ARM: dts: rockchip: add more iommu nodes on rk3288Simon Xue1-0/+37
Add IEP/ISP/VPU/HEVC iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-06ARM: dts: rockchip: convert rk3288 device tree files to 64 bitsTao Huang1-89/+89
In order to be able to use more than 4GB of RAM when the LPAE is activated, the dts must be converted in 64 bits. Signed-off-by: Tao Huang <huangtao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-07-16ARM: dts: rockchip: fix mali gpu node on rk3288Heiko Stuebner1-2/+2
The binding specifies the actual implementations only (mali-t760 for example) but not the arm,mali-midgard used in some vendor kernels. So drop that compatible property from the rk3288 where it had slipped in. Also fix the node name which should be a generic gpu@... Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-19ARM: dts: rockchip: add ARM Mali GPU node for rk3288Guillaume Tucker1-0/+43
Add Mali GPU device tree node for the rk3288 SoC, with devfreq opp table. Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-16ARM: dts: rockchip: add rk3288 dw-mmc resetsHeiko Stuebner1-0/+8
dw-mmc got its reset-properties specified, so add the softresets for it in rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviwed-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-02-07ARM: DTS: Fix register map for virt-capable GICMarc Zyngier1-1/+1
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-01-02ARM: dts: rockchip: add qos node for rk3288Elaine Zhang1-0/+84
when pd power on/off, the qos regs need to save and restore. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-12-15Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-6/+8
Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together. We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board: - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors These are commercially available consumer platforms we now support: - Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385 And a couple of new boards targeted at developers, makers or industrial integration: - Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module Other changes: - added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq - Continued fixes for W=1 dtc warnings - The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST - The exynos4415 dtsi file is removed as nothing uses it. - Intel PXA25x can now be booted using devicetree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...
2016-11-18usb: dwc2: Deprecate g-use-dma bindingJohn Youn1-1/+0
This is not needed as the gadget now fully supports DMA and it can autodetect it. This was initially added because gadget DMA mode was only partially implemented so could not be automatically enabled. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-09ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"Jaehoon Chung1-4/+4
In drivers/mmc/core/host.c, there is "max-frequency" property. It should be same behavior. So use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-16ARM: dts: rockchip: update compatible strings for Rockchip efuseFinley Xiao1-1/+1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-16ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsiJavier Martinez Canillas1-1/+3
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-07Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-32/+41
Pull ARM DT updates from Arnd Bergmann: "These are as usual a very large number of mostly boring updates to enable devices in existing machines, or to fix minor bugs. Notably, an ongoing treewide effort to fix warnings caused by an update to the device tree compiler. These are enabled with "make W=1" at the moment but can hopefully become the default once all issues have been addressed. No new SoC platform is added this time around (Armada 395 and Orion mv88f5181 are slight variations of existing ones), but a significant number of new dts files are added, which I list by platform: - Allwinner: Empire Electronix M712 and iNet d978 Rev2 tablets, Orange Pi PC Plus, Orange Pi 2, Orange Pi Plus 2E, Orange Pi Lite, Olimex A33-Olinuxino, and Nano Pi Neo single-board computers - ARM Realview: all supported machines (ported from board files) - Broadcom: BCM958525er, BCM958522er, BCM988312hr, BCM958623hr and BCM958622hr reference boards for Northstar platform, Raspberry Pi Zero single-board computer - Marvell EBU: Netgear WNR854T router (ported from board file), Armada 395 SoC platform and GP board Armada 390 DB development board - NXP i.MX: imx7s Warp7 reference board, Gateworks Ventana GW553x single-board computer, Technologic Systems TS-4900 and Engicam IMX6UL GEA M6UL computer-on-module, Inverse Path USB armory board - Qualcomm: LG Nexus 5 Phone - Renesas: r8a7792/wheat and r7s72100/rskrza1 development boards - Rockchip: Rockchip RK3288 Fennec reference board, Firefly RK3288 Reload platform - ST Microelectronics STi: B2260 (96boards) single-board computer - TI Davinci: OMAP-L138 LCDK Development kit - TI OMAP: beagleboard-x15 rev B1 single-board computer" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (390 commits) ARM: dts: sony-nsz-gs7: add missing unit name to /memory node ARM: dts: chromecast: add missing unit name to /memory node ARM: dts: berlin2q-marvell-dmp: add missing unit name to /memory node ARM: dts: berlin2: Add missing unit name to /soc node ARM: dts: berlin2cd: Add missing unit name to /soc node ARM: dts: berlin2q: Add missing unit name to /soc node ARM: dts: berlin2: Remove skeleton.dtsi inclusion ARM: dts: berlin2cd: Remove skeleton.dtsi inclusion ARM: dts: berlin2q: Remove skeleton.dtsi inclusion arm: dts: berlin2q: enable all wdt nodes unconditionally arm: dts: berlin2: enable all wdt nodes unconditionally ARM: dts: omap5-igep0050.dts: Use tabs for indentation ARM: dts: Fix igepv5 power button GPIO direction ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node ARM: dts: s3c64xx: Use macros for pinctrl configuration ARM: dts: s3c2416: Use macros for pinctrl configuration ARM: dts: s5pv210: Use macros for pinctrl configuration ARM: dts: s3c64xx: Use common macros for pinctrl configuration ...
2016-08-23arm: dts: rockchip: add reset node for the exist saradc SoCsCaesar Wang1-0/+2
SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2016-08-11ARM: dts: rockchip: add syscon-reboot-mode DT nodeAndy Yan1-0/+10
Rockchip platform use a SYSCON mapped register store the reboot mode magic value for bootloader to use when system reboot. So add syscon-reboot-mode driver DT node for rk3xxx/rk3036/rk3288 based platform Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-08ARM: dts: rockchip: move rk3288 usbphy under the GRF nodeHeiko Stuebner1-32/+31
The rk3288 usbphy is completely enclosed in the general register files and the updated binding allows it to be a subnode of the GRF now. So move the node appropriately. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-01Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+5
Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is: New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792 Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...
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