aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/socfpga_arria10.dtsi (follow)
AgeCommit message (Collapse)AuthorFilesLines
2015-10-06ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10Dinh Nguyen1-0/+8
Add the required clock fields for all the I2C nodes. Also add missing clock fields for UART0 and USB1. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-13Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dtOlof Johansson1-0/+6
SoCFPGA DTS updates for v4.3, take 2 - Add DTS property "altr,modrst-offset" for reset driver to use - Add updated reset defines for the reset driver - Add reset property for EMACs on Arria10 * tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: Add resets for EMACs on Arria10 ARM: socfpga: dts: add "altr,modrst-offset" property dt-bindings: Add reset manager offsets for Arria10 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-09ARM: socfpga: dts: Add resets for EMACs on Arria10Dinh Nguyen1-0/+5
Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-09ARM: socfpga: dts: add "altr,modrst-offset" propertyDinh Nguyen1-0/+1
The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20ARM: dts: socfpga: use stdout-path for chosen nodeDinh Nguyen1-0/+5
Use stdout-path dts property for kernel console. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-26Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-16/+336
Pull ARM SoC DT updates from Kevin Hilman: "As usual, quite a few device-tree updates in ARM land. There was one minor churn in DTs due to relicensing under a dual-license, and lots of little additions of new peripherals, features etc, but nothing really exciting to call to your attention. Some higlights, focsuing on support for new SoCs and boards: - AT91: new boards: Overkiz, Acme Systems' Arietta G25 - tegra: HDA support - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys boards, DLink DNS-327L - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50 - ARM: added support for Juno r1 board - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6, Gateworks GW5510, and aristainetos2 boards - hisilicon: hi6220 SoC support; new boards: 96boards hikey" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits) ARM: hisi: revert changes from hisi/hip04-dt branch ARM: nomadik: set proper compatible for accelerometer ARM64: juno: add GPIO keys ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes ARM: dts: Introduce STM32F429 MCU ARM: socfpga: dts: enable ethernet for Arria10 devkit ARM: dts: k2l: fix the netcp range size ARM: dts: k2e: fix the netcp range size ARM: dts: k2hk: fix the netcp range size ARM: dts: k2l-evm: Add device bindings for netcp driver ARM: dts: k2e-evm: Add device bindings for netcp driver ARM: dts: k2hk-evm: Add device bindings for netcp driver ARM: BCM5301X: Add DT for Asus RT-AC87U ARM: BCM5301X: add IRQ numbers for PCIe controller ARM: BCM5301X: add NAND flash chip description arm64: dts: Add dts files for Hisilicon Hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC ARM: at91/dt: sama5d4ek: mci0 uses slot 0 ARM: at91/dt: kizbox: fix mismatch LED PWM device ...
2015-06-24arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS supportThor Thayer1-0/+11
Add support for the Arria10 SDRAM EDAC. Update the bindings document for the new match string. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2015-06-10ARM: socfpga: dts: enable ethernet for Arria10 devkitDinh Nguyen1-0/+11
Update the arria10 gmac nodes with all the necessary properties for ethernet to function on the Arria10 devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10Merge tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dtKevin Hilman1-0/+6
SoCFPGA updates for v4.2 part 3 - Add SCU node for Arria 10 - Add enable-method for cpu nodes - Add SDRAM controller binding doc - Enable gpio-leds on SoCFPGA Socrates board * tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: socrates: add gpio-leds ARM: socfpga: socrates: enable gpio0/1 ARM: socfpga: dts: add sdram controller dt binding doc ARM: socfpga: dts: add enable-method property for cpu nodes ARM: socfpga: dts: add the a9-scu node for arria10
2015-06-02ARM: socfpga: dts: add enable-method property for cpu nodesDinh Nguyen1-0/+1
Add the enable-method property for the cpu node on socfpga.dtsi and socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable the secondary core. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02ARM: socfpga: dts: add the a9-scu node for arria10Dinh Nguyen1-0/+5
Add a dts node for the A9 SCU on the Arria10 platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11ARM: socfpga: dts: add clocks to the Arria10 platformDinh Nguyen1-4/+305
Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-05-11ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth propertiesVince Bridgers1-0/+4
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga stmmac. These devicetree properties will be used to configure certain features of the stmmac on the socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11ARM: socfpga: dts: Add multicast bins and unicast filter entriesVince Bridgers1-0/+6
Add multicast-filter-bins and perfect-filter-entries configuration properties to the socfpga devicetree for the Arria 10 socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11ARM: socfpga: dts: enable UART1 for the debug uartDinh Nguyen1-12/+0
Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add removal of unused aliases
2015-05-11ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10Dinh Nguyen1-0/+3
Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11ARM: socfpga: dts: add cpu1-start-addr for Arria 10Dinh Nguyen1-0/+1
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-11-20arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOCDinh Nguyen1-0/+374
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.