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2018-09-29ARM: dts: sun8i: h3-h5: ir register size should be the whole memory blockPhilipp Rossak1-1/+1
The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embed3d@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-07-19ARM: dts: sunxi-h3-h5: Remove unused address-cells/size-cells of dwmac-sun8iCorentin Labbe1-2/+0
address-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-20ARM: dts: sunxi: h3/h5: Add r_i2c I2C controllerOndrej Jirman1-0/+13
Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman <megous@megous.com> [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-04-20ARM: dts: sunxi: h3/h5: Add r_i2c pinmux nodeOndrej Jirman1-0/+5
H3/H5 SoCs contain an I2C controller optionally available on the PL0 and PL1 pins. This patch adds pinmux configuration for this controller. Signed-off-by: Ondrej Jirman <megous@megous.com> [Icenowy: change commit message, node name and function name] Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-03-02ARM: dts: sunxi: h3/h5: Add HDMI pipelineJernej Skrabec1-0/+108
This commit adds all entries needed for HDMI to function properly. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-02-15ARM: dts: sunxi: h3-h5: rename mmc0_pins_a and mmc1_pins_aJoonas Kylmälä1-4/+4
There is only one pinctrl configuration for mmc0 and mmc1 so let's drop the _a suffix from both of them. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-02-15ARM: dts: sunxi: h3-h5: Move pinctrl of mmc1 from dts to dtsiJoonas Kylmälä1-0/+2
Most of the boards use the mmc1 pins and their attributes defined in mmc1_pins_a. Let's default to that by moving the pinctrl attributes to the dtsi file. This makes it easier to modify device trees in the future as there is only one place to change the pinctrl attributes. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-02-14ARM: dts: sunxi: h3-h5: Move pinctrl of mmc0 from dts to dtsiJoonas Kylmälä1-0/+2
Most of the boards use the mmc0 pins and their attributes defined in mmc0_pins_a. Let's default to those by moving the pinctrl attributes to the dtsi file. This makes it easier to modify device trees in the future as there is only one place to change the pinctrl attributes. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-02-14ARM: dts: sunxi: h3-h5: remove mmc0 card detection pin from pinctrlJoonas Kylmälä1-6/+0
The GPIO card detection pin (mmc0_cd_pin) is already requested and configured by mmc_gpiod_request_cd() in drivers/mmc/core/slot-gpio.c so pinctrl is not needed. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-01-03ARM: sunxi: h3/h5: add simplefb nodesIcenowy Zheng1-0/+24
The H3/H5 SoCs have a HDMI output and a TV Composite output. Add simplefb nodes for these outputs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-12-29ARM: sun8i: h3/h5: add DE2 CCU device node for H3Icenowy Zheng1-0/+14
The DE2 in H3/H5 has a clock control unit in it, and the behavior is slightly different between H3 and H5. Add the common parts in H3/H5 DTSI, and add the compatible string in H3 DTSI. The compatible string of H5 DE2 CCU will be added in a separated patch. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-11-02ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emacCorentin Labbe1-4/+27
Since dwmac-sun8i could use either an integrated PHY or an external PHY (which could be at same MDIO address), we need to represent this selection by a MDIO switch. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-11-02arm: dts: sunxi: h3/h5: Restore EMAC changesCorentin Labbe1-0/+26
The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore sunxi-h3-h5.dtsi This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-09-26ARM: dts: sunxi: h3/h5: Fix node with unit name and no reg propertyCorentin LABBE1-6/+6
This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-09-26ARM: dts: sunxi: h3/h5: Fix i2c2 register addressCorentin LABBE1-1/+1
The unit address and register address does not match. This patch fix the register address with the good one. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-09-26ARM: dts: sunxi: h3/h5: Fix simple-bus unit address format errorCorentin LABBE1-37/+37
This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-09-17ARM: dts: sunxi: h3/h5: Add DAI nodesMarcus Cooper1-0/+26
Add the new DAI blocks to the device tree. I2S0 and I2S1 are for connecting to an external codec. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-09-17ARM: dts: sun8i: h3: Adding UART3 RTS and CTS PinsPhilipp Rossak1-0/+5
This node adds the definition for the UART3 RTS and CTS Pins That makes it able to use UART3 with RTS and CTS. Signed-off-by: Philipp Rossak <embed3d@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-08-28arm: dts: sunxi: Revert EMAC changesMaxime Ripard1-26/+0
Since the discussion is not settled yet for the EMAC, and that the release in getting really close, let's revert the changes for now, and we'll reintroduce them later. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-07-27ARM: dts: sunxi: h3/h5: Correct emac register sizeCorentin Labbe1-1/+1
The datasheet said that emac register size is 0x10000 not 0x104 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Fixed commit subject prefix] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-07-04Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-3/+45
Pull ARM device-tree updates from Arnd Bergmann: "Device-tree continues to see lots of updates. The majority of patches here are smaller changes for new hardware on existing platforms, and there are a few larger changes worth pointing out. New machines: - The new Action Semi S500 platform is added along with initial support for the LeMaker Guitar board. - STM32 gains support for three new boards: stm32h743-disco, stm32f746-disco, and stm32f769-disco, along with new device support for the existing stm32f429 boards. - Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with 10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus board. - On Marvell "mvebu", we gain support for the Linksys WRT3200ACM wireless router. - For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and the Technexion Pico i.MX7D single-board computers. - The BeagleBone Blue is added for OMAP, it's the latest variation of the popular Beaglebone Black single-board computer. - The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are added, these are the latest variations of a seemingly endless supply of similar single-board computers. Other updates: - Linus Walleij improves support for the "Faraday" based SoC platforms from various SoC makers (Moxart, Aspeed, Gemini) - The ARM Mali GPU is now describe on Rockchips SoCs - Mediatek MT7623 is extended significantly, making it much more useful. - Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom, Allwinner, Qualcomm, iMX - For Amlogic, the clock support is extended a lot on meson8b. - We now build the devicetree file for the Raspberry Pi 3 on 32-bit ARM, in addition to the existing ARM64 support, to help users wanting to run a 32-bit system on it" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits) ARM: dts: socfpga: set the i2c frequency ARM: dts: socfpga: Add second ethernet alias to VINING FPGA ARM: dts: socfpga: Drop LED node from VINING FPGA ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA ARM: dts: socfpga: Enable QSPI support on VINING FPGA ARM: dts: socfpga: Fix the ethernet clock phandle ARM: pxa: Use - instead of @ for DT OPP entries ARM: dts: owl-s500: Add SPS node ARM: dts: owl-s500: Set CPU enable-method dt-bindings: arm: cpus: Add S500 enable-method ARM: dts: Add Actions Semi S500 and LeMaker Guitar dt-bindings: arm: Document Actions Semi S900 dt-bindings: timer: Document Owl timer ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes dt-bindings: arm: Document Actions Semi S500 dt-bindings: Add vendor prefix for Actions Semi ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango) ARM: dts: armada-385-linksys: fixup button node names ARM: dts: armada-385-linksys: group pins in pinctrl ...
2017-06-06arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driverCorentin Labbe1-0/+34
The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree. SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-06arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control moduleCorentin Labbe1-0/+6
This patch add the dt node for the syscon register present on the Allwinner H3/H5 Only two register are present in this syscon and the only one useful is the one dedicated to EMAC clock.. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-06ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macrosChen-Yu Tsai1-3/+5
Now that the R_CCU device tree binding headers have been merged, we can convert the raw number references in the device trees to use the defined macros. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-03ARM: sunxi: h3-h5: Add PLL_PERIPH0 clock to the R_CCUChen-Yu Tsai1-2/+3
The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of its parents. This adds the reference in the device tree describing this relationship. This patch uses a raw number for the clock index to ease merging by avoiding cross tree dependencies. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-14ARM: sunxi: h3/h5: fix the compatible of R_CCUIcenowy Zheng1-1/+1
The R_CCU of H3/H5 currently wrongly used A64 R_CCU compatible. Fix it by changing it to the correct H3 compatible. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-04ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccuIcenowy Zheng1-31/+14
Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5Icenowy Zheng1-0/+32
Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller. Add device nodes for these controllers. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27arm: sun8i: h3: split Allwinner H3 .dtsiAndre Przywara1-0/+586
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller updated. So we should really share almost the whole .dtsi. In preparation for that move the peripheral parts of the existing sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi. The actual sun8i-h3.dtsi then includes that and defines the H3 specific parts on top of it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Icenowy: also split out mmc and gic, as well as pio and ccu's compatible, and make drop of skeleton into a seperated patch] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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