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2021-09-19ARM: dts: qcom: apq8064: adjust memory node according to specsDavid Heidelberg1-1/+1
Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210908172544.55666-1-david@ixit.cz
2021-09-19ARM: dts: qcom: apq8064: Convert adreno from legacy gpu-pwrlevels to opp-v2David Heidelberg1-6/+10
APQ8064 was last user of gpu-pwrlevels inside mainline tree, so convert it now. Tested on Nexus 7 2013, no functional changes. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829133918.57780-3-david@ixit.cz
2021-09-19ARM: dts: qcom: apq8064: update Adreno clock namesDavid Heidelberg1-4/+4
The legacy clock names (including the _clk suffix) was dropped from the driver, so update the dts accordingly). Tested on Nexus 7 2013, no functional changes. Signed-off-by: David Heidelberg <david@ixit.cz> [bjorn: Updated commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829133918.57780-2-david@ixit.cz
2021-09-17arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodesRob Herring6-44/+26
The 'motherboard-bus' node in Arm Ltd boards fails schema checks as 'simple-bus' child nodes must have a unit-address. The 'ranges' handling is also wrong (or at least strange) as the mapping of SMC chip selects should be in the 'arm,vexpress,v2m-p1' node rather than a generic 'simple-bus' node. Either there's 1 too many levels of 'simple-bus' nodes or 'ranges' should be moved down a level. The latter change is more simple, so let's do that. As the 'ranges' value doesn't vary for a given motherboard instance, we can move 'ranges' into the motherboard dtsi files. Link: https://lore.kernel.org/r/20210819184239.1192395-6-robh@kernel.org Cc: Andre Przywara <andre.przywara@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-15ARM: dts: at91: add Exegin Q5xR5 boardOwen Kirby2-0/+200
Add Exegin Q5xR5. The base device tree is from OpenWrt tree and with the addition of this patch there will be no need to maintain it separatelly in OpenWrt. [osk: original author of patch in OpenWrt] [claudiu.beznea: use "&<label> {" syntax, sorted nodes in alphabetical order, adapted flash to new support in kernel 5.14, use proper compatibles according to kernel 5.14, use macros instead of hardcoded numbers for pinctrl phandles and for all pinctrl references, add pinctrl-names, pinctrl-X where necessaray] Signed-off-by: Owen Kirby <osk@exegin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210816064416.1630674-8-claudiu.beznea@microchip.com
2021-09-15ARM: dts: at91: add CalAmp LMU5000 boardAdam Porter2-0/+148
Add CalAmp LMU5000 board. The base device tree is from OpenWrt tree and with the addition of this patch there will be no need to maintain it separatelly in OpenWrt. [porter.adam: original author of patch in OpenWrt] [claudiu.beznea: fixed compilation warnings, use &<lable> syntax, sorted nodes in alphabetical order, adapted flash to new support in kernel 5.14, use proper compatibles according to kernel 5.14, use macros instead of hard coded numbers for pinctrl phandles and for all pinctrl references, add pinctrl-names, pinctrl-X where necessary] Signed-off-by: Adam Porter <porter.adam@gmail.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210816064416.1630674-5-claudiu.beznea@microchip.com
2021-09-15ARM: dts: at91: at91sam9260: add pinctrl labelClaudiu Beznea1-1/+1
Add label for pinctrl node. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210816064416.1630674-2-claudiu.beznea@microchip.com
2021-09-15ARM: dts: at91-sama5d27_som1_ek: Added I2C bus recovery supportDurai Manickam KR2-3/+32
SDA and SCL is configured as GPIO for I2C bus to recover during I2C bus malfunction. Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210914052113.85695-1-durai.manickamkr@microchip.com
2021-09-15ARM: dts: at91: sama7g5ek: enable ADC on the boardEugen Hristev1-0/+8
The ADC controller on the board is fed by a 2.5V reference voltage. By default the channels #14 and #15 are dedicated to analog input (marked AN on the board), on the connectors mikrobus1 and mikrobus2. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210901123013.329792-11-eugen.hristev@microchip.com
2021-09-15ARM: dts: at91: sama7g5: add node for the ADCEugen Hristev1-0/+16
Add node for the ADC controller in sama7g5 SoC. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210901123013.329792-10-eugen.hristev@microchip.com
2021-09-15ARM: dts: at91: sama5d27_wlsom1: add wifi deviceEugen Hristev1-0/+70
SAMA5D27 WLSOM1 boards has a WILC3000 device soldered. Add proper device tree nodes for this. [eugen.hristev: original author of this code] [claudiu.beznea: adapt such that make dtbs_check is happy, remove status for wifi_pwrseq and wifi nodes] Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [nicolas.ferre: original author of this code] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20210825094055.642941-1-claudiu.beznea@microchip.com
2021-09-15ARM: dts: exynos: drop undocumented samsung,sata-freq property in Exynos5250Krzysztof Kozlowski1-1/+0
The samsung,sata-freq property is not used (and not documented by generic AHCI platform bindings), so can be safely dropped. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210811083859.28234-2-krzysztof.kozlowski@canonical.com
2021-09-14ARM: dts: BCM5301X: Specify switch ports for more devicesRafał Miłecki6-0/+232
Those are remaining models I have that didn't have ports yet. All tested. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Fix MX65 MDIO mux warningsMatthew Hagan2-3/+5
The naming of this node is based upon that of the initial EA9500 dts[1]. However this does not conform with the mdio-mux format, yielding the following message when running dtbs_check: mdio-mii-mux: $nodename:0: 'mdio-mii-mux' does not match '^mdio-mux[\\-@]?' Secondly, this node should be moved to within the axi node and given the appropriate unit address. This also requires exposing the axi node via a label in bcm-nsp.dtsi. This fixes the following warning: Warning (unit_address_vs_reg): /mdio-mii-mux: node has a reg or ranges property, but no unit name [1]https://patchwork.ozlabs.org/project/linux-imx/patch/20180618174159.86150-1-npcomplete13@gmail.com/#1941353 Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Fix MX64/MX65 eeprom node nameMatthew Hagan1-1/+1
Running dtbs_check yields the following message when checking the MX64/MX65 devicetree: at24@50: $nodename:0: 'at24@50' does not match '^eeprom@[0-9a-f]{1,2}$' This patch fixes the issue by renaming the at24 node appropriately. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Fix MDIO mux node namesMatthew Hagan2-2/+2
While functional, the mdio-mux-mmioreg binding does not conform to Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml in that an mdio-mux compatible is also required. Without this the following output is observed when running dtbs_check: mdio-mux@32000: compatible: ['mdio-mux-mmioreg'] is too short This change brings conformance to this requirement and corresponds likewise to Rafal Milecki's change to the BCM5301x platform[1]. [1] https://lore.kernel.org/linux-arm-kernel/20210822191256.3715003-1-f.fainelli@gmail.com/T/ Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Fix mpcore, mmc node namesMatthew Hagan1-2/+2
Running dtbs_check yielded the issues with bcm-nsp.dtsi. Firstly this patch fixes the following message by appending "-bus" to the mpcore node name: mpcore@19000000: $nodename:0: 'mpcore@19000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Secondly mmc node name. The label name can remain as is. sdhci@21000: $nodename:0: 'sdhci@21000' does not match '^mmc(@.*)?$' Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Add bcm958623hr board name to dtsMatthew Hagan1-1/+1
This board was previously added to Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml however the dts file was not updated to reflect this change. This patch corrects bcm958623hr.dts by adding the board name to the compatible. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: BCM5301X: Fix memory nodes namesRafał Miłecki11-11/+11
Thix fixes: arch/arm/boot/dts/bcm4708-netgear-r6250.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 134217728]]} arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 134217728]]} arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 402653184]]} arch/arm/boot/dts/bcm4709-linksys-ea9200.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 134217728]]} arch/arm/boot/dts/bcm4709-netgear-r7000.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 134217728]]} arch/arm/boot/dts/bcm4709-netgear-r8000.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 134217728]]} arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728]]} arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728], [2281701376, 402653184]]} arch/arm/boot/dts/bcm53016-meraki-mr32.dt.yaml: /: memory: False schema does not allow {'reg': [[0, 134217728]], 'device_type': ['memory']} arch/arm/boot/dts/bcm94708.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728]]} arch/arm/boot/dts/bcm94709.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 134217728]]} Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: BCM5301X: Fix MDIO mux bindingRafał Miłecki1-1/+1
This fixes following error for all BCM5301X dts files: mdio-bus-mux@18003000: compatible: ['mdio-mux-mmioreg'] is too short Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: BCM5301X: Fix nodes namesRafał Miłecki2-5/+5
This fixes following errors for all BCM5301X dts files: chipcommonA@18000000: $nodename:0: 'chipcommonA@18000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' mpcore@19000000: $nodename:0: 'mpcore@19000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' mdio-bus-mux@18003000: $nodename:0: 'mdio-bus-mux@18003000' does not match '^mdio-mux[\\-@]?' dmu@1800c000: $nodename:0: 'dmu@1800c000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Add DT files for Meraki MX65 seriesMatthew Hagan4-0/+337
MX65 & MX65W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 switch (2x 1GbE ports) 2x Qualcomm QCA8337 switches (10x 1GbE ports total) - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. Note that a driver and firmware image for the BCM59111 PSE has been released under GPL, but this is not present in the kernel. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Add DT files for Meraki MX64 seriesMatthew Hagan6-0/+281
MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Add Ax stepping modificationsMatthew Hagan1-0/+70
While uncommon, some Ax NSP SoCs exist in the wild. This stepping requires a modified secondary CPU boot-reg and removal of DMA coherency properties. Without these modifications, the secondary CPU will be inactive and many peripherals will exhibit undefined behaviour. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Add common bindings for MX64/MX65Matthew Hagan1-0/+129
These bindings are required for all Meraki MX64/MX65 devices. These common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND partitions, EHCI, OHCI and pinctrl. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: Move USB3 PHY to internal MDIO busMatthew Hagan1-7/+31
This patch largely replicates Vivek Unune's patch "ARM: dts: BCM5301X:Make usb3 phy use mdio phy driver"[1] for the NSP platform, whereby we need to create an mdio-mux to facilitate switches configured via external MDIO, in this case on the Meraki MX65. However in doing so, we are creating an overlap with usb3_phy's ccb-mii range. To resolve this, usb3_phy should be moved to a child node of the internal MDIO bus. The result is heavily based upon Vivek's patch. This has also been cross-referenced with Yendapally Reddy's earlier work which utilised the subsequently dropped brcm,nsp-usb3-phy driver: "[PATCH v2 4/4] arm: dts: nsp: Add USB nodes to device tree" [2]. Finally, this change provides conformance to the bcm-ns-usb3-phy documentation, utilising the required usb3-dmp-syscon property. Note that support for the deprecated ccb-mii bindings has been dropped as of "phy: phy-bcm-ns-usb3: drop support for deprecated DT binding"[3]. [1] https://lore.kernel.org/patchwork/patch/933971/ [2] https://www.spinics.net/lists/arm-kernel/msg555132.html [3] https://lore.kernel.org/linux-devicetree/20201113113423.9466-1-zajec5@gmail.com/ Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: add MDIO bus controller nodeMatthew Hagan1-0/+7
This patch adds the node for the MDIO bus controller, present on the NSP SoC. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: disable qspi node by defaultMatthew Hagan9-0/+9
The QSPI bus is enabled by default, however this may not used on all devices. This patch disables by default, requiring it to be explicitly enabled where required. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: enable DMA on bcm988312hrMatthew Hagan1-0/+4
The previous patch "ARM: dts: NSP: Disable PL330 by default, add dma-coherent property" set the DMAC to disabled by default, requiring it to be manually enabled on each device. The bcm988312hr was mistakenly omitted. This patch adds it back. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: NSP: add device names to compatibleMatthew Hagan7-7/+7
Currently only the SoC type and platform are specified for all NSP devices. This patch adds the device names. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-14ARM: dts: ux500: Tag Janice display SPI correctLinus Walleij1-0/+3
The s6e63m0 display used "type 3" SPI communication so flag the device as using negative clocking and polarity on the SPI bus. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-09-14ARM: dts: at91: sama5d2_som1_ek: disable ISC node by defaultEugen Hristev1-1/+0
Without a sensor node, the ISC will simply fail to probe, as the corresponding port node is missing. It is then logical to disable the node in the devicetree. If we add a port with a connection to a sensor endpoint, ISC can be enabled. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210902121358.503589-1-eugen.hristev@microchip.com
2021-09-14ARM: dts: at91: sama7g5: add chipidClaudiu Beznea1-0/+5
Add chipid node for sama7g5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210908094329.182477-1-claudiu.beznea@microchip.com
2021-09-14ARM: dts: at91: sama7g5: add shdwc nodeClaudiu Beznea2-0/+20
Add shutdown controller node and enable it. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com
2021-09-14ARM: dts: at91: sama7g5: add securam nodeClaudiu Beznea1-0/+11
Add securam node. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210823131915.23857-4-claudiu.beznea@microchip.com
2021-09-14ARM: dts: at91: sama7g5: add ram controllersClaudiu Beznea1-0/+12
Add RAM and RAMC PHY controllers. These are necessary for platform specific power management code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com
2021-09-14arm: dts: vexpress-v2p-ca9: Fix the SMB unit-addressRob Herring2-2/+2
Based on 'ranges', the 'bus@4000000' node unit-address is off by 1 '0'. Link: https://lore.kernel.org/r/20210819184239.1192395-5-robh@kernel.org Cc: Andre Przywara <andre.przywara@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-14arm: dts: vexpress: Drop unused properties from motherboard nodeRob Herring2-5/+0
Drop the '#interrupt-cells' property in the motherboard node which has no effect as the node is neither an interrupt-controller or interrupt-map (that's in the parent node). Drop 'model' as it is not used by software nor documented. Drop 'arm,v2m-memory-map' as it is not used by software. The purpose was to describe which memory map, but that's all described by the DT already. Link: https://lore.kernel.org/r/20210819184239.1192395-4-robh@kernel.org Cc: Andre Przywara <andre.przywara@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-14ARM: dts: arm: align watchdog and mmc node names with dtschemaKrzysztof Kozlowski1-2/+2
Align the watchdog and mmc device node names with the schema to fix warnings like: mmci@50000: $nodename:0: 'mmci@50000' does not match '^mmc(@.*)?$' wdt@f0000: $nodename:0: 'wdt@f0000' does not match '^watchdog(@.*|-[0-9a-f])?$' Link: https://lore.kernel.org/r/20210820081733.83976-2-krzysztof.kozlowski@canonical.com Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-14ARM: dts: everest: Add 'factory-reset-toggle' as GPIOF6Isaac Kurth1-1/+2
The state of this GPIO determines whether a factory reset has been requested. If a physical switch is used, it can be high or low. During boot, the software checks and records the state of this switch. If it is different than the previous recorded state, then the read-write portions of memory are reformatted. Signed-off-by: Isaac Kurth <isaac.kurth@ibm.com> Link: https://lore.kernel.org/r/20210901185236.558771-1-isaac.kurth@ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-14ARM: dts: aspeed: everest: Add I2C bus 15 muxesEddie James1-0/+158
Add the muxes that are attached on I2C bus 15. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210903214836.48286-3-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-14ARM: dts: aspeed: rainier: Add system LEDsEddie James1-12/+1121
Add all the missing system LEDs. These are all connected by GPIO expanders. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210903214836.48286-2-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-14ARM: dts: aspeed: amd-ethanolx: Add FRU EEPROMKonstantin Aladyshev1-0/+5
AMD EthanolX CRB uses 24LC128 EEPROM chip to store its FRU information. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20210909132053.3919-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-14ARM: dts: fp5280g2: Enable KCS 3 for MCTP bindingGeorge Liu1-0/+7
Signed-off-by: George Liu <liuxiwei@inspur.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210819055227.140980-1-liuxiwei@inspur.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-13ARM: dts: qcom: Add support for LG G Watch RLuca Weiss2-0/+238
Add a device tree for the LG G Watch R smartwatch, manufactured by LG Electronics and based on the msm8226 platform (apq8026). Currently UART, internal storage, power button and touchscreen are supported. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> [bjorn: Moved "rpm_requests" before "sdhc", to keep things sorted] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210911232707.259615-9-luca@z3ntu.xyz
2021-09-13ARM: dts: qcom: Add pm8226 PMICLuca Weiss1-0/+27
The pm8226 is used with Qualcomm platforms, like msm8226. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210911232707.259615-6-luca@z3ntu.xyz
2021-09-13ARM: dts: qcom: msm8226: Add more SoC bitsLuca Weiss1-8/+255
Add nodes for sdhc, uart4, i2c, scm, smem, rpm-requests including dependencies. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> [bjorn: Moved other nodes before "soc" to keep things alphabetical] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210911232707.259615-5-luca@z3ntu.xyz
2021-09-13ARM: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL referenceMarijn Suijten1-2/+2
The 28NM DSI PLL driver for msm8960 calculates with a 27MHz reference clock and should hence use PXO, not CXO which runs at 19.2MHz. Note that none of the DSI PHY/PLL drivers currently use this "ref" clock; they all rely on (sometimes inexistant) global clock names and usually function normally without a parent clock. This discrepancy will be corrected in a future patch, for which this change needs to be in place first. Fixes: 6969d1d9c615 ("ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210829203027.276143-2-marijn.suijten@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-09-13ARM: dts: qcom: apq8064: use compatible which contains chipidDavid Heidelberg1-2/+1
Also resolves these kernel warnings for APQ8064: adreno 4300000.adreno-3xx: Using legacy qcom,chipid binding! adreno 4300000.adreno-3xx: Use compatible qcom,adreno-320.2 instead. Tested on Nexus 7 2013, no functional changes. Cc: <stable@vger.kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210818065317.19822-1-david@ixit.cz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-09-13ARM: dts: sun8i: r40: Add I2S nodesJernej Skrabec1-0/+39
Allwinner R40 has 3 I2S controllers, compatible to those in H3. First two are routed to pins, while third is used internally for HDMI audio. Add nodes for all 3 I2S controllers. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210912072914.398419-3-jernej.skrabec@gmail.com
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