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The rng11 is not available on the STiH418 hence is disabled in the
stih418.dtsi
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The STiH407 family (and further versions STiH410/STiH418) embedded
a serial flash controller allowing fast access to SPI-NOR.
This commit adds the corresponding node, relying on the st-spi-fsm
drivers.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, Switch BeagleBone boards to use new cpsw switch driver. Those boards
have or 2 Ext. port wired and configured in dual_mac mode by default, or
only 1 Ext. port.
For am335x-sancloud-bbe-common.dtsi also removed duplicated davinci_mdio DT
nodes which already defined in am335x-bone-common.dtsi.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Update ethernet aliases to point at CPSW switchdev driver.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Toby Churchill SL50 Series to use new cpsw switch driver.
Those boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Bosch SHC to use new cpsw switch driver.
Those boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Phytec AM335x phyCORE SOM, phyBOARD-WEGA, phyBOARD-REGOR,
PCM-953 to use new cpsw switch driver. Those boards have or 2 Ext. port
wired and configured in dual_mac mode by default, or only 1 Ext. port.
Cc: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Gumstix Pepper to use new cpsw switch driver.
Those boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch EETS,PDU001 to use new cpsw switch driver. Those boards have or
2 Ext. port wired and configured in dual_mac mode by default, or only 1
Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Octavo Systems OSD3358-SM-RED to use new cpsw switch driver.
Those boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch MYIR MYC-AM335X/MYD-AM335X to use new cpsw switch driver. Those
boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Cc: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Moxa am335x-moxa-uc-210x/8100 to use new cpsw switch driver.
Those boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Cc: Johnson Chen <johnsonch.chen@moxa.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch NovaTech OrionLXm to use new cpsw switch driver. Those boards
have or 2 Ext. port wired and configured in dual_mac mode by default, or
only 1 Ext. port
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch am335x-igep0033 to use new cpsw switch driver. Those boards have
or 2 Ext. port wired and configured in dual_mac mode by default, or only 1
Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch CompuLab CM-T335 to use new cpsw switch driver. Those boards
have or 2 Ext. port wired and configured in dual_mac mode by default, or
only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch AM335x Chiliboard to use new cpsw switch driver. Those boards
have or 2 Ext. port wired and configured in dual_mac mode by default, or
only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch Newflow AM335x NanoBone to use new cpsw switch driver. Those
boards have or 2 Ext. port wired and configured in dual_mac mode by
default, or only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, switch OnRISC Baltos and NetCom/Cam boards to use new cpsw switch
driver. Those boards have or 2 Ext. port wired and configured in dual_mac
mode by default, or only 1 Ext. port.
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add GMAC_AHB_RESET to the resets property of each gmac node.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Link: https://lore.kernel.org/r/20210605173546.4102455-2-mnhagan88@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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This file is licensed in some kind of BSD manner, put it under
the combined GPL+BSD license like what the bindings use, it
seems most helpful.
I wrote the whole file so whatever. Those are my principles,
if you don't like them: I have others.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210409124954.320529-1-linus.walleij@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Castor has a BCM4339 attached to BLSP2 UART7, add the necessary nodes to
define the uart as well as the serdev BCM.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Julian Weigt <juw@posteo.de>
Link: https://lore.kernel.org/r/20210723202101.65371-2-juw@posteo.de
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Julian Weigt <juw@posteo.de>
Link: https://lore.kernel.org/r/20210723202101.65371-1-juw@posteo.de
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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PPD has only one ACHC device, which effectively is a Kinetis
microcontroller. It has one SPI interface used for normal
communication. Additionally it's possible to flash the device
firmware using NXP's EzPort protocol by correctly driving a
second chip select pin and the device reset pin.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20210802172309.164365-3-sebastian.reichel@collabora.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Describe Exynos5422 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-7-krzysztof.kozlowski@canonical.com
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Describe Exynos5420 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-6-krzysztof.kozlowski@canonical.com
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Describe Exynos5260 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-5-krzysztof.kozlowski@canonical.com
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Describe Exynos5250 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-4-krzysztof.kozlowski@canonical.com
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Describe Exynos4412 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-3-krzysztof.kozlowski@canonical.com
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Describe Exynos4210 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-2-krzysztof.kozlowski@canonical.com
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Describe Exynos3250 CPU topology.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210731092409.31496-1-krzysztof.kozlowski@canonical.com
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MT7623/BPI-R2 has idle temperature after bootup from 48 degrees celsius
increase the passive trip temp threshold to not trottle CPU frequency at
this temperature
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20210725163451.217610-1-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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AT91 dt for 5.15:
- add sama7g5 SoC and associated evaluation kit, the sama7g5-ek
- adaptation of some DT for sama5d27 som1 ek, sama5d4 xplained and
sama5d2 icp boards
- fixes to gpio and shutdown controller nodes for all boards
* tag 'at91-dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: use the right property for shutdown controller
ARM: dts: at91: sama5d2_icp: enable digital filter for I2C nodes
ARM: dts: at91: sama5d4_xplained: change the key code of the gpio key
ARM: dts: at91: add conflict note for d3
ARM: dts: at91: add pinctrl-{names, 0} for all gpios
ARM: dts: at91: sama5d27_som1_ek: enable ADC node
ARM: dts: at91: sama5d4_xplained: Remove spi0 node
dt-bindings: atmel-sysreg: add bindings for sama7g5
ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek
dt-bindings: ARM: at91: document sama7g5ek board
Link: https://lore.kernel.org/r/20210804085000.13233-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Ux500 Device Tree updates for the v5.15 kernel cycle:
- New device trees for these mobile phones:
- Samsung Gavini
- Samsung Codina
- Samsung Kyle
- Flag eMMC cards as non-SD non-SDIO to save time
- Link USB PHY to USB controller in the device tree
- Fix up the operating points to the actual clock frequencies
* tag 'ux500-dts-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ux500: Adjust operating points to reality
ARM: dts: ux500: Add a device tree for Kyle
ARM: dts: ux500: Add devicetree for Codina
ARM: dts: ux500: ab8500: Link USB PHY to USB controller node
ARM: dts: ux500: Flag eMMCs as non-SDIO/SD
ARM: dts: ux500: Add device tree for Samsung Gavini
Link: https://lore.kernel.org/r/CACRpkdbjBv5ywZZD8rK07d5sLcHsG8o4iYD-3jHO=HLg6-nKnA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Fixes for omaps for v5.14-rc series
Some fixes for regressions and boot issues for various devices:
- Fix gpt12 system timer regression on earlier beagleboard revisions
- Fix potential NULL pointer access for omap_hwmod_get_pwrdm()
- Disable RNG on secure am335x variants as it's not accessible
- Fix flakey DCDC2 voltage causing hangs on am43x-epos-evm by reducing
i2c0 bus speed for tps65218
- Fix typo for am437x-l4 can@0 node
- Fix omap5 regression caused by vdds_1v8_main fixed-regulator
* tag 'omap-for-v5.14/fixes-rc5-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
omap5-board-common: remove not physically existing vdds_1v8_main fixed-regulator
ARM: dts: am437x-l4: fix typo in can@0 node
ARM: dts: am43x-epos-evm: Reduce i2c0 bus speed for tps65218
bus: ti-sysc: AM3: RNG is GP only
ARM: omap2+: hwmod: fix potential NULL pointer access
bus: ti-sysc: Fix gpt12 system timer issue with reserved status
Link: https://lore.kernel.org/r/pull-1627995895-406133@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The PRUSSs on AM57xx SoCs contain an MDIO controller that can
be used to control external PHYs associated with the Industrial
Ethernet peripherals within each PRUSS. The MDIO module used
within the PRU-ICSS is an instance of the MDIO Controller used
in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as
the regular MDIO node.
The nodes are added in the common am57-pruss.dtsi file and enabled
by default, but are disabled in all the existing AM57xx board dts
files. These nodes need pinctrl lines, and so should be enabled
only on boards where they are actually wired and pinned out for
PRUSS Ethernet. Any new board dts file should disable these if
they are not sure.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add the DT nodes for the PRU-ICSS1 and PRU-ICSS2 processor subsystems
that are present on AM57xx family of SoCs. Each PRU-ICSS instance is
represented by a pruss node and other child nodes. The two PRU-ICSSs
are identical to each other. They are not supported on DRA7xx SoCs in
general, so the nodes are added under the respective interconnect target
module nodes in a common am57-pruss.dtsi file. The file is already
included only in the AM57xx related board files.
The PRU-ICSSs on AM57xx are very similar to the PRUSS in AM33xx and AM437x
except for variations in the RAM sizes and the number of interrupts coming
into the MPU INTC. The interrupt events into the PRU-ICSS also requires
programming of the corresponding crossbars properly.
The PRUSS subsystem node contains the entire address space. The various
sub-modules of the PRU-ICSS are represented as individual child nodes
(so platform devices themselves) of the PRUSS subsystem node. These
include the two PRU cores and the interrupt controller. All the Data
RAMs are represented within a child node of its own named 'memories'
without any compatible. The Real Time Media Independent Interface
controller (MII_RT), and the CFG sub-module are represented as syscon
nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk
node is added under the CFG child node 'clocks'. The default source
for this mux clock is the ICSS_IEP_CLK clock.
The DT nodes use all standard properties. The regs property in the PRU
nodes define the addresses for the Instruction RAM, the Debug and Control
sub-modules for that PRU core. The firmware for each PRU core is defined
through a 'firmware-name' property.
The default names for the firmware images for each PRU core are defined
as follows (these can be adjusted either in derivative board dts files or
through sysfs at runtime if required):
PRU-ICSS1 PRU0 Core: am57xx-pru1_0-fw
PRU-ICSS1 PRU1 Core: am57xx-pru1_1-fw
PRU-ICSS2 PRU0 Core: am57xx-pru2_0-fw
PRU-ICSS2 PRU1 Core: am57xx-pru2_1-fw
Note:
1. There are few more sub-modules like the Industrial Ethernet Peripheral
(IEPs), MDIO, UART, eCAP that do not have bindings and so will be added
in the future.
2. The PRUSS INTC on AM57xx SoCs also connect the host interrupts 6 and 7
as possible DMA events, so use the 'ti,irqs-reserved' property in
derivative board dts files _if_ any of them should not be handled by
the host OS.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The PRU-ICSS1 instance on AM437x SoCs has a MDIO sub-module that
can be used to control external PHYs associated with the Industrial
Ethernet peripherals within the PRUSS. The MDIO module used within
this PRU-ICSS is an instance of the MDIO Controller used in TI
Davinci SoCs. The same bus frequency of 1 MHz is chosen as the
regular MDIO node. Note that there is no MDIO node added to the
smaller PRU-ICSS0 instance as the MDIO pins are not pinned out.
The node is added and enabled in the common am4372.dtsi file by
default, and disabled in all the existing AM437x board dts files.
This node needs pinctrl lines, and so should be enabled only on
boards where they are actually wired and pinned out for PRUSS
Ethernet. Any new board dts file should disable these if they
are not sure.
Signed-off-by: Andrew F. Davis <afd@ti.com>
[s-anna@ti.com: fix reg address, add commit description]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The AM4376+ SoCs have a second smaller PRU-ICSS subsystem (PRUSS0) in
addition to the primary PRUSS1 instance. The PRUSS0 has less DRAM
per PRU, and no Shared DRAM among other minor differences. The IEP
and MII_RT modules even though present within the IP are not pinned
out.
This PRUSS0 instance has a weird SoC integration. It shares the same
L3 OCP interconnect interface with PRUSS1, and also shares its reset
line and clocks. Any external accesses from PRUSS0 requires the PRUSS1's
PRUSS_SYSCFG register to be programmed properly. That said, it is its
own IP instance (a cut-down version), and so it has been added as an
independent node (sibling node to PRUSS1 node) and a child node of the
corresponding PRUSS target module interconnect node. This allows the
PRUSS0 instance to be enabled/disabled independently of the PRUSS1
instance.
The nodes are added under the corresponding interconnect target module
node in the common am4372 dtsi file. The PRU-ICSS instances are not
supported on AM4372 SoC though in the AM437x family, so the interconnect
target module node should be disabled in any derivative board dts file that
uses AM4372 SoCs. The individual PRUSS node can be disabled in the
corresponding board dts file if desired.
The default names for the firmware images for each PRU core are defined
as follows (these can be adjusted either in derivative board dts files or
through sysfs at runtime if required):
PRU-ICSS0 PRU0 Core: am437x-pru0_0-fw
PRU-ICSS0 PRU1 Core: am437x-pru0_1-fw
Note:
1. There are few more sub-modules like the Industrial Ethernet Peripheral
(IEP), eCAP, UART, that do not have bindings and so will be added in the
future. Only UART is pinned out, so others should be added in disabled
state if added.
2. The PRUSS0 INTC on AM437x SoCs routes the host interrupt 5 to the other
PRUSS1, so it is already marked reserved through the 'ti,irqs-reserved'
property.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add the DT node for the PRU-ICSS1 instance on the AM437x family of SoCs.
Each PRU-ICSS instance is represented by a pruss node and other child
nodes. The nodes are added under the interconnect target module node in
the common am4372 dtsi file. The PRU-ICSS instances are supported only
on AM4376+ SoCs though in the AM437x family, so the interconnect target
module node should be disabled in any derivative board dts file that
uses AM4372 SoCs.
The PRU-ICSS1 on AM437x is very similar to the PRUSS in AM33xx, except
for variations in the RAM sizes, bus addresses and the number of
interrupts coming into the MPU INTC (host interrupt 5 is routed to
the other PRUSS instead of MPU).
The PRUSS subsystem node contains the entire address space. The various
sub-modules of the PRU-ICSS are represented as individual child nodes
(so platform devices themselves) of the PRUSS subsystem node. These
include the two PRU cores and the interrupt controller. All the Data
RAMs are represented within a child node of its own named 'memories'
without any compatible. The Real Time Media Independent Interface
controller (MII_RT), and the CFG sub-module are represented as syscon
nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk
node is added under the CFG child node 'clocks'. The default source
for this mux clock is the PRU_ICSS_IEP_GCLK clock.
The DT nodes use all standard properties. The regs property in the PRU
nodes define the addresses for the Instruction RAM, the Debug and Control
sub-modules for that PRU core. The firmware for each PRU core is defined
through a 'firmware-name' property.
The default names for the firmware images for each PRU core are defined
as follows (these can be adjusted either in derivative board dts files
or through sysfs at runtime if required):
PRU-ICSS1 PRU0 Core: am437x-pru1_0-fw
PRU-ICSS1 PRU1 Core: am437x-pru1_1-fw
Note:
1. There are few more sub-modules like the Industrial Ethernet Peripheral
(IEP), MDIO, UART, eCAP that do not have bindings and so will be added
in the future.
2. The PRUSS INTC on AM437x SoCs also connect the host interrupt 0 to ADC0
and ADC1; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved'
property in derivative board dts files _if_ any of them should not be
handled by the host OS. Host interrupt 5 is already marked reserved as
it is connected to the other PRUSS instance.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The PRU-ICSS target module node was left in disabled state in the
base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x ICEv2
board, so enable this node to support PRUSS on this board. The PRUSS
node and most of its child nodes are already enabled in the base dts
file, and so become effective automatically with the enabling of
this PRU-ICSS target module node.
The corresponding PRU nodes can be disabled later on if there are
no use-cases defined to use a particular PRU core or the whole
PRU-ICSS subsystem itself if both its PRU cores are unused.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The PRU-ICSS target module node was left in disabled state in the
base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x SK
EVM board, so enable this node to support PRUSS on this board. The
PRUSS node and most of its child nodes are already enabled in the
base dts file, and so become effective automatically with the
enabling of this PRU-ICSS target module node.
The corresponding PRU nodes can be disabled later on if there are
no use-cases defined to use a particular PRU core or the whole
PRU-ICSS subsystem itself if both its PRU cores are unused.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Alain Volmat
Grygorii Strashko
Matthew Hagan
Linus Walleij
Bjorn Andersson
Craig Tatlor
Sebastian Reichel
Krzysztof Kozlowski
Frank Wunderlich
Arnd Bergmann
Suman Anna
Andrew F. Davis