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2020-09-02ARM: dts: exynos: Align SPI GPIO node name with dtschema in Universal C210Krzysztof Kozlowski1-1/+1
The device tree schema expects SPI controller to be named "spi", otherwise dtbs_check complain with a warning like: arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: spi-lcd: $nodename:0: 'spi-lcd' does not match '^spi(@.*|-[0-9a-f])*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-13-krzk@kernel.org
2020-09-02ARM: dts: exynos: Add and enable 32 kHz modem clock in TratsKrzysztof Kozlowski1-0/+5
The PMIC has a 32768 Hz clock used by the modem which is implemented by driver as a regulator. Add and enable it to be sure modem get's its signal. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-10-krzk@kernel.org
2020-09-02ARM: dts: exynos: Add and enable 32 kHz modem clock in Galaxy I9100Krzysztof Kozlowski1-0/+5
The PMIC has a 32768 Hz clock used by the modem which is implemented by driver as a regulator. Add and enable it to be sure modem get's its signal. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-8-krzk@kernel.org
2020-09-02ARM: dts: exynos: Correct S3C RTC bindings in SMDKv310Krzysztof Kozlowski1-0/+12
The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround - a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-smdkv310.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-smdkv310.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-7-krzk@kernel.org
2020-09-02ARM: dts: exynos: Correct S3C RTC bindings and enable it in Universal C210Krzysztof Kozlowski1-0/+13
The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround - add a fixed-clock to fill missing clock phandle reference in S3C RTC. The "clock" regulator in PMIC is already present and enabled. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20200830135200.24304-6-krzk@kernel.org
2020-09-02ARM: dts: exynos: Correct S3C RTC bindings and enable it in TratsKrzysztof Kozlowski1-0/+18
The S3C RTC requires 32768 Hz clock as input which is provided by PMIC (Maxim MAX8997). However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround: 1. Enable the "clock" regulator in PMIC, 2. Add a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-trats.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-trats.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20200830135200.24304-5-krzk@kernel.org
2020-09-02ARM: dts: exynos: Correct S3C RTC bindings and enable it in OrigenKrzysztof Kozlowski1-0/+14
The S3C RTC requires 32768 Hz clock as input which is provided by PMIC (Maxim MAX8997). However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround: 1. Enable the "clock" regulator in PMIC, 2. Add a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-origen.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-origen.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20200830135200.24304-4-krzk@kernel.org
2020-09-02ARM: dts: exynos: Correct S3C RTC bindings and enable it in Galaxy I9100Krzysztof Kozlowski1-0/+18
The S3C RTC requires 32768 Hz clock as input which is provided by PMIC (Maxim MAX8997). However there is no clock provided for the PMIC and the driver registers the clock as regulator. This is an old driver which will not be updated so add a workaround: 1. Enable the "clock" regulator in PMIC, 2. Add a fixed-clock to fill missing clock phandle reference in S3C RTC. This allows to enable the S3C RTC and fixes dtbs_check warnings: arch/arm/boot/dts/exynos4210-i9100.dt.yaml: rtc@10070000: clocks: [[5, 346]] is too short arch/arm/boot/dts/exynos4210-i9100.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-3-krzk@kernel.org
2020-09-02ARM: dts: exynos: Correct GPU regulator properties in Galaxy I9100Krzysztof Kozlowski1-2/+1
The regulator property 'regulator-microvolt-offset' should be put next to regulator definition, not consumer. The property 'regulator-microsecs-delay' is not valid at all. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-2-krzk@kernel.org
2020-09-02ARM: dts: exynos: Silence i2c-gpio dtschema warning in Galaxy I9100Krzysztof Kozlowski1-1/+1
The name of I2C controller over GPIO lines node ends with '-gpio' which confuses dtschema: /arch/arm/boot/dts/exynos4210-i9100.dt.yaml: /: i2c-gpio: {'compatible': ['i2c-gpio'], ... 'maxim,over-volt': [[4500]]}} is not of type 'array' From schema: lib/python3.6/site-packages/dtschema/schemas/gpio/gpio-consumer.yaml Add a '-0' suffix to silence it. This pattern on naming i2c-gpio is already present in many other dts. No functional change. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200830135200.24304-1-krzk@kernel.org
2020-09-02ARM: dts: exynos: Remove snps, dwc2 compatible in Exynos3250Krzysztof Kozlowski1-1/+1
The binding for DesignWare HS OTG USB 2.0 in Samsung SoCs take only one compatible. This fixes dtbs_check warnings like: arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml: hsotg@12480000: compatible: ['samsung,s3c6400-hsotg', 'snps,dwc2'] is not valid under any of the given schemas (Possible causes of the failure): Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200829172532.29358-4-krzk@kernel.org
2020-09-01ARM: dts: exynos: Move fixed clocks under root node in Exynos3250Krzysztof Kozlowski1-25/+17
The fixed clocks are kept under dedicated node fixed-rate-clocks, thus a fake "reg" was added. This is not correct with dtschema as fixed-clock binding does not have a "reg" property: arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml: clock@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20200829172532.29358-2-krzk@kernel.org
2020-09-01arm/boot: Handle all sections explicitlyKees Cook1-10/+10
In preparation for warning on orphan sections, use common macros for debug sections, discards, and text stubs. Add discards for unwanted .note, and .rel sections. Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Russell King <linux@armlinux.org.uk> Link: https://lore.kernel.org/r/20200821194310.3089815-21-keescook@chromium.org
2020-08-31ARM: dts: r8a7742-iwg21m: Add SPI NOR supportLad Prabhakar1-0/+51
Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200825085435.8744-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-31ARM: dts: imx6qdl-gw553x: Remove unneeded #address-cells/#size-cellsFabio Estevam1-2/+0
The following dtc warning is seen when building with W=1: arch/arm/boot/dts/imx6qdl-gw553x.dtsi:65.12-110.4: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the unneeded #address-cells/#size-cells properties to fix the issue. Fixes: 64bf0a0af18d ("ARM: dts: imx6qdl-gw: add Gateworks System Controller support") Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-31ARM: dts: imx6sll-evk: Add audio sound card nodeShengjiu Wang1-0/+73
Add audio sound card node, which depends on codec node, SSI node, audmux node. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-31ARM: dts: imx6sl-evk: Add headphone detection for sound cardShengjiu Wang1-0/+9
Headphone detection is triggered by GPIO, then driver can switch between speaker and headphone. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-31ARM: dts: imx6sx-sdb: Add headphone detection for sound cardShengjiu Wang1-0/+9
Headphone detection is triggered by GPIO, then driver can switch between speaker and headphone. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-30ARM: dts: rockchip: replace status value "ok" by "okay"Adrian Schmutzler8-8/+8
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Link: https://lore.kernel.org/r/20200830190820.20583-1-freifunk@adrianschmutzler.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-08-30ARM: dts: rockchip: update cpu supplies on rk3066aJohan Jonker3-3/+15
The use of cpu0-supply for cpu0 alone is deprecated, so add cpu-supply to each cpu separately and update all existing rk3066a boards. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200813172451.13754-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-08-30ARM: dts: rockchip: rk3066a: add label to cpu@1Johan Jonker1-1/+1
Add label to cpu@1 for later use. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200813172451.13754-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-08-30ARM: dts: rockchip: update cpu supplies on rk3288Johan Jonker4-4/+52
The use of cpu0-supply for cpu0 alone is deprecated, so add cpu-supply to each cpu separately and update all existing rk3288 boards that use this property. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200813180241.14660-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-08-30ARM: dts: ux500-skomer: Add KTD253 backlightLinus Walleij1-9/+6
This enables the KTD253 backlight found on the Samsung GT-S7710 "Skomer". Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200828223034.40983-1-linus.walleij@linaro.org
2020-08-30ARM: dts: imx6q-kontron-samx6i: Remove old fsl,spi-num-chipselectsKrzysztof Kozlowski1-1/+0
The property "fsl,spi-num-chipselects" is gone since commit 790739c4417c ("dt-bindings: spi: Convert imx cspi to json-schema"). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-30ARM: dts: imx: Fix the SPI chipselect polarityFabio Estevam56-81/+82
The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-28ARM: dts: ux500-golden: Add S6E63M0 DSI displayLinus Walleij1-0/+91
Add the Samsung S6E63M0 video mode DSI display to the Samsung GT-S8190/Golden mobile phone. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200815102627.3532646-1-linus.walleij@linaro.org
2020-08-27ARM: dts: sun8i: r40: Add node for system controllerJernej Skrabec1-0/+23
Allwinner R40 has system controller and SRAM C1 region similar to that in A10. Add nodes for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825173523.1289379-3-jernej.skrabec@siol.net
2020-08-27ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable IRJernej Skrabec1-0/+4
BananaPi M2 Ultra has IR receiver connected to IR0. Enable it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825171358.1286902-4-jernej.skrabec@siol.net
2020-08-27ARM: dts: sun8i: r40: Add IR nodesJernej Skrabec1-0/+36
Allwinner R40 has two IR cores, add nodes for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825171358.1286902-3-jernej.skrabec@siol.net
2020-08-26ARM: dts: BCM5301X: Specify pcie2 in the DTChristian Lamparter1-0/+4
The SoC supports three pcie ports. Currently, only pcie0 and pcie1 are enabled. This patch adds the pcie2 port as well. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-08-26ARM: dts: BCM5301X: Specify uart2 in the DTChristian Lamparter1-0/+9
The BCM53016 in the Meraki MR32 utilizes the third "uart2" to connect to a on-board Bluetooth-LE 4.0 BCM20732 chip. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-08-26ARM: dts: BCM5301X: Specify PWM in the DTChristian Lamparter1-2/+10
The BCM53016 in the Meraki MR32 uses the on-chip PWM controller to drive a tri-color RGB LED. Since I plan to use the PWM, I made a label for the pwm's pinmux node. This way, it can be easily referenced.... And Also included a label for the i2c since I'm going to need it in the future too. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-08-25ARM: at91: Add GARDENA smart Gateway (Art. 19000) supportReto Schneider2-0/+159
This patch adds support for the GARDENA smart Gateway, which is based on the Atmel AT91SAM9G25. It is equipped with 128 MiB of DDR2 RAM and 256 MiB NAND storage. Please note that this gateway is not actually based on a AT91SAM9x5 EK board, but is close enough to allow its DT to be used. Co-developed-by: Stefan Roese <sr@denx.de> Co-developed-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net> Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200822151023.31629-2-code@reto-schneider.ch
2020-08-25ARM: dts: sun8i: r40: Add DMA nodeJernej Skrabec1-0/+12
Allwinner R40 SoC has DMA with 16 channels and 31 request sources. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825100030.1145356-3-jernej.skrabec@siol.net
2020-08-25ARM: dts: r8a7742-iwg21m: Add RTC supportLad Prabhakar1-0/+20
Enable BQ32000 RTC which is connected to I2C0 on the iWave RainboW-G21M-q7 SOM. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200816193316.7641-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-25ARM: dts: r8a7742-iwg21m: Sort the nodes alphabeticallyLad Prabhakar1-7/+7
Sort the DT nodes alphabetically so that its easier to maintain. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200816193316.7641-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-25ARM: dts: r8a7742: Add CAN supportLad Prabhakar1-0/+34
Add the definitions for can0 and can1 to the r8a7742 SoC dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-25ARM: dts: sun4i: Enable HDMI support on the Mele A1000Stefan Monnier1-0/+25
Enable the display pipeline and HDMI output. Signed-off-by: Stefan Monnier <monnier@iro.umontreal.ca> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200821171833.28177-1-monnier@iro.umontreal.ca
2020-08-25ARM: dts: sun8i: r40: Add Mali nodeJernej Skrabec1-0/+22
R40 has Mali400 GP2 GPU. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200824150434.951693-3-jernej.skrabec@siol.net
2020-08-25ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulatorJernej Skrabec1-5/+5
DCDC1 regulator powers many different subsystems. While some of them can work at 3.0 V, some of them can not. For example, VCC-HDMI can only work between 3.24 V and 3.36 V. According to OS images provided by the board manufacturer this regulator should be set to 3.3 V. Set DCDC1 and DCDC1SW to 3.3 V in order to fix this. Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200824193649.978197-1-jernej.skrabec@siol.net
2020-08-25ARM: dts: aspeed: rainier: Enable XDMA engineEddie James1-3/+9
Fix the VGA reserved memory node, and add the XDMA engine node, enable it, and point it's memory region to the VGA memory. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: wedge40: Update UART4 pin settingsTao Ren1-1/+2
Enable UART4's NRTS4 (A19) pin because the pin is used for RS485 software emulation. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Link: https://lore.kernel.org/r/20200824182955.7988-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: wedge40: Update FMC flash0 labelTao Ren1-1/+1
Update FMC flash0's label to "spi0.0" so it's consistent with all the other Facebook OpenBMC platforms. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Link: https://lore.kernel.org/r/20200824182955.7988-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: Add Facebook Wedge400 BMCTao Ren2-0/+421
Add initial version of device tree for Facebook Wedge400 (AST2500) BMC. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200824211948.12852-6-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: minipack: Update 64MB FMC flash layoutTao Ren1-2/+45
Set 64Mb FMC flash layout in Minipack device tree explicitly because the flash layout was removed from "ast2500-facebook-netbmc-common.dtsi". Please note "data0" partition' size is updated to 4MB to be consistent with other Facebook OpenBMC platforms. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Link: https://lore.kernel.org/r/20200824211948.12852-5-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: yamp: Set 32MB FMC flash layoutTao Ren1-0/+17
Set 32MB FMC flash layout in Yamp device tree explicitly because flash layout settings were removed from "ast2500-facebook-netbmc-common.dtsi". Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Link: https://lore.kernel.org/r/20200824211948.12852-4-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: cmm: Set 32MB FMC flash layoutTao Ren1-0/+17
Set 32MB FMC flash layout in CMM device tree explicitly because the flash layout settings were removed from "ast2500-facebook-netbmc-common.dtsi". Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Link: https://lore.kernel.org/r/20200824211948.12852-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-25ARM: dts: aspeed: Remove flash layout from Facebook AST2500 Common dtsiTao Ren1-13/+0
Remove FMC flash layout from ast2500-facebook-netbmc-common.dtsi because flash size and layout varies across different Facebook AST2500 OpenBMC platforms. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Link: https://lore.kernel.org/r/20200824211948.12852-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-24ARM: dts: meson: move the L2 cache-controller inside the SoC nodeMartin Blumenstingl1-7/+7
All IO mapped SoC peripherals should be within the "soc" node. Move the L2 cache-controller there as well since it's the only one not following this pattern. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200815182223.408965-1-martin.blumenstingl@googlemail.com
2020-08-24Merge tag 'imx-fixes-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesOlof Johansson7-11/+9
i.MX fixes for 5.9: - Fix QuadSPI-memory 'reg' for LS1021A and GPIO 'ranges' for i.MX7ULP pinctrl. - A couple of DTC warning fixes on imx6qdl-gw51xx and imx6q-prtwd2 boards. - Add missing imx8mm-beacon-kit.dtb to dtbs-y for build coverage. - Fix broken PWM settings on imx6q-logicpd board. - Add missing syscon compatible to OCOTP device, so that access to UID is possible. - Fix a network regression on imx7d-zii-rmu2 due to a phy-mode mismatch. * tag 'imx-fixes-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx7d-zii-rmu2: fix rgmii phy-mode for ksz9031 phy ARM: dts: vfxxx: Add syscon compatible with OCOTP ARM: dts: imx6q-logicpd: Fix broken PWM arm64: dts: imx: Add missing imx8mm-beacon-kit.dtb to build ARM: dts: imx6q-prtwd2: Remove unneeded i2c unit name ARM: dts: imx6qdl-gw51xx: Remove unneeded #address-cells/#size-cells ARM: dts: imx7ulp: Correct gpio ranges ARM: dts: ls1021a: fix QuadSPI-memory reg range Link: https://lore.kernel.org/r/20200824130359.GF12776@dragon Signed-off-by: Olof Johansson <olof@lixom.net>
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