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2019-11-01ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pinsKarl Palsson1-0/+5
uart1 and uart3 had existing pin definitions for the rts/cts pairs. Add definitions for uart2 as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun9i: a80: Add Security System nodeCorentin Labbe1-0/+9
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A80 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun8i: a83t: Add Security System nodeCorentin Labbe1-0/+9
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A83T SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun8i: H3: Add Crypto Engine nodeCorentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun8i: R40: add crypto engine nodeCorentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic offloader that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: aspeed: tacoma: Enable FMC and SPI devicesJoel Stanley1-0/+31
Tacoma has two SPI flash devices attached to the FMC, and one on the SPI controller. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: rainier: Add i2c devicesBrad Bishop1-0/+365
Add fan controllers, regulators, temperature sensors, power supplies and regulators. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Describe FSI mastersJoel Stanley1-0/+20
The ast2600 has two FSI masters on the APB. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: Add "spi-max-frequency" propertyCédric Le Goater7-1/+20
Keep the FMC controller chips at a safe 50 MHz rate and use 100 MHz for the PNOR on the machines using a AST2500 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: Migrate away from aspeed, g[45].* compatiblesAndrew Jeffery2-2/+2
Use the SoC-specific compatible strings instead. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: vesnin: Add power_green ledAlexander Filippov1-0/+4
Adds a new power_green led to show the host state. Signed-off-by: Alexander Filippov <a.filippov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: tacoma: Add gpio-key definitionsEddie James1-0/+60
Add gpio-keys for various signals on Tacoma. Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: ast2600-evb: Add pinmux properties for enabled MACsAndrew Jeffery1-0/+9
All 2600-evb MACs use RGMII/MDIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Add pinctrl properties to MDIO nodesAndrew Jeffery1-0/+8
This way enabling the MDIO controllers automatically requests the right pinmux configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Fix EMMC function in pinctrl dtsiAndrew Jeffery1-7/+2
The binding was updated to better reflect the intended use of the hardware and the existing function/groups for SD3 were dropped. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: ast2600evb: Use custom flash layoutJoel Stanley1-1/+31
The AST2600 u-boot and kernel images have outgrown the OpenBMC layout. While BMC machines use 128MB SPI NOR chips, we only have 64MB on the EVB so use a layout that has a smaller region for the ro and rw filesystems. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: ast2600-evb: Enable FMC and SPI devicesCédric Le Goater1-0/+24
Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: tacoma: Enable FMC and SPI devicesJoel Stanley1-0/+31
Tacoma has two SPI flash devices attached to the FMC, and one on the SPI controller. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: rainier: Enable FMC and SPI devicesCédric Le Goater1-0/+31
Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: rainier: Add i2c devicesBrad Bishop1-0/+365
Add fan controllers, regulators, temperature sensors, power supplies and regulators. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: rainier: Add mac devicesBrad Bishop1-0/+14
Rainier contains two NCSI network devices. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: Add Rainier systemBrad Bishop2-0/+54
Rainier is a new IBM server with POWER host processors and an AST2600 BMC. Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: Add 128MiB OpenBMC flash layoutBrad Bishop1-0/+32
This is an alternate layout used by OpenBMC systems that require more space on the BMC's flash. In addition to more space for the rootfs, it supports a larger u-boot and Linux kernel FIT image. The division of space is as follows: u-boot + env: 1MB kernel/FIT: 9MB rwfs: 86MB rofs: 32MB Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: fp5280g2: Add LED configurationChicago Duan1-15/+40
Change BMC init-ok from GPIO to LED, which needs to blink when BMC initialization is complete. Use TAB to align some lines. Signed-off-by: Chicago Duan <duanzhijia01@inspur.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: tacoma: Enable I2C bussesEddie James1-0/+368
Enable all the I2C busses on Tacoma and add the I2C slave devices that exist on the busses. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed: Add Tacoma machineJoel Stanley2-0/+442
This is an AST2600 based BMC card for a Power9 system. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Add FMC and SPI devicesCédric Le Goater1-0/+79
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Add lpc devicesBrad Bishop1-0/+87
Everything is the same as G5, except the devices have their own interrupt now. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Add VUART descriptionsJoel Stanley1-0/+22
The AST2600 has two VUART devices. Reviewed-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Add i2c busesJoel Stanley1-0/+266
The AST2600 has 16 I2C buses each with their own global IRQ line. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: aspeed-g6: Add gpio devicesRashmica Gupta1-0/+26
The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs. Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01ARM: dts: ast2600-evb: eMMC configurationAndrew Jeffery2-3/+9
Enable the eMMC controller and limit it to 52MHz to avoid the host controller reporting bus error conditions. Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-10-31ARM: dts: omap3: fix DPLL4 M4 divider max valueTero Kristo2-1/+5
The maximum divider value for DPLL4 M4 divider appears wrong. For most OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe only valid for omap36xx. To avoid any overflows in trying to write this register, set the max to 16 for all omap3 family, except omap36xx. For omap36xx the maximum is set to 31, as it appears value 32 is not working properly. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com>
2019-10-31ARM: dts: sun8i: a83t: a711: Add touchscreen nodeMylène Josserand1-0/+16
Enable a FocalTech EDT-FT5x06 Polytouch touchscreen. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-31ARM: dts: rockchip: Add HDMI audio support to rk3288-veyron-mickeyCheng-Yi Chiang1-0/+7
Add HDMI audio support to veyron-mickey. The sound card should expose one audio device for HDMI. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Link: https://lore.kernel.org/r/20191028071930.145899-7-cychiang@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-31ARM: dts: rockchip: Add HDMI support to rk3288-veyron-analog-audioCheng-Yi Chiang1-0/+1
All boards using rk3288-veyron-analog-audio.dtsi have HDMI audio. Specify the support of HDMI audio on machine driver using rockchip,hdmi-codec property so machine driver creates HDMI audio device. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Link: https://lore.kernel.org/r/20191028071930.145899-6-cychiang@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-30Merge branch 'rng' into omap-for-v5.5/dtTony Lindgren4-1/+37
2019-10-30ARM: dts: Configure omap3 rngTony Lindgren4-1/+37
Looks like omap3 RNG is similar to the omap2 rng, let's get it working by configring the dts node for it. We must also add rng_ick to core_l4_clkdm as noted by Adam Ford. And please note that the RNG is likely disabled on HS devices. At least n900 does not have it accessible, and instead omap3-rom-rng driver must be used. So let's tag RNG as disabled on n900 as noted by Pali Rohár <pali.rohar@gmail.com>. On am3517 at least the clocks need to be configured to get it working as noted by Adam Ford, so let's tag it disabled for now. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Adam Ford <aford173@gmail.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Sebastian Reichel <sre@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com> #logicpd-torpedo-37xx-devkit Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-10-29ARM: tegra: cardhu-a04: Add CPU Operating Performance PointsDmitry Osipenko1-0/+24
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on Cardhu A04. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: cardhu-a04: Set up voltage regulators for DVFSDmitry Osipenko1-0/+24
Set minimum and maximum voltages, and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: trimslice: Add CPU Operating Performance PointsDmitry Osipenko1-0/+11
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available now on TrimSlice. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: paz00: Add CPU Operating Performance PointsDmitry Osipenko1-0/+14
Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on AC100. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: paz00: Set up voltage regulators for DVFSDmitry Osipenko1-7/+20
Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add CPU Operating Performance Points for Tegra30Dmitry Osipenko2-0/+2003
Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary for them. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add CPU Operating Performance Points for Tegra20Dmitry Osipenko2-0/+503
Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary, like for example in a case of tegra20-trimslice which is outlet-powered device. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add Tegra30 CPU clockDmitry Osipenko1-0/+4
All "geared" CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add Tegra20 CPU clockDmitry Osipenko1-0/+2
All CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add External Memory Controller node on Tegra30Dmitry Osipenko1-0/+9
Add External Memory Controller node to the device-tree. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6Dmitry Osipenko1-1621/+6248
Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1, which was missed due to the clock driver bug that is fixed now in all of stable kernels. Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30Dmitry Osipenko1-0/+1
Enable IOMMU support for the video decoder. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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