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2019-03-27ARM: dts: rskrza1: Add I2C supportGeert Uytterhoeven1-0/+33
Enable the I2C bus, and add the following devices: - Two CAT9554 port expanders (8 GPIOs, interrupt not wired by default), - R1EX24016ASAS0A EEPROM. The bus also contains a MAX9856 Audio Codec, which is not yet supported. All devices (incl. the audio codec) are documented to support an I2C bus running at 400 kHz. Pinctrl is based on the RZ/A BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-26ARM: dts: sun7i: fix typos in uart pin muxMans Rullgard1-4/+4
The recently added uart mux options had a few typos. Fix them. Fixes: 43d0fe112585 ("ARM: dts: sun7i: add pinctrl for missing uart mux options") Reported-by: Werner Böllmann <Werner.Boellmann@fh-dortmund.de> Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: dts: sun9i: Remove deprecated pinctrl propertiesMaxime Ripard1-5/+4
We switched to the generic pinctrl binding some time ago, yet the GMAC pinctrl node apparently slipped through. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: dts: sun8i: h3: Add default dr_modeMaxime Ripard1-0/+1
The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: dts: Fix dcan clkctrl clock for am3Tony Lindgren1-2/+2
We must not use legacy clock defines for dts clckctrl clocks as the offsets will be wrong. Fixes: 87fc89ced3a7 ("ARM: dts: am335x: Move l4 child devices to probe them with ti-sysc") Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: dts: imx7ulp: add ocotp supportAnson Huang1-0/+6
Add i.MX7ULP OCOTP support, its clock source is from M4 BUS clock which is NOT available in Linux clock tree, but M4 BUS clock is always ON when A7 (Linux) is alive, so just use dummy clock here. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-26ARM: dts: Add devicetree for Eckelmann ci4x10Uwe Kleine-König2-0/+382
This is one of two boards that make use of the recently introduced SIOX bus. Apart from the devices described in the dts it features a display with touch that I didn't include here because it needs some non-mainline change to operate correctly. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-26ARM: dts: stm32: add initial support of stm32mp157c-dk2 boardAlexandre Torgue2-0/+76
Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2). This board is a "super-set" of stm32mp157a-dk1. It embeds a STM32MP157c SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Same connections than stm32mp157a-dk1 board are available. Display panel (otm8009a) and Murata wifi/BT combo is added. This patch adds basic support for a kernel boot and enable otm8009a display panel. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-03-26ARM: dts: stm32: add initial support of stm32mp157a-dk1 boardAlexandre Torgue2-0/+78
Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1). This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Several connections are available on this boards: 4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ... This patch enables basic support for a kernel boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-03-25ARM: dts: sunxi: Add default dr_modeMaxime Ripard6-0/+6
The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: A23/A33: Fix pinctrl node namesMaxime Ripard1-5/+5
The NAND pinctrl nodes names don't follow the pattern we've used and enforced for some time. Make sure they do. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Remove pinctrl size-cells propertyMaxime Ripard2-2/+0
The children nodes of the pinctrl node hadn't have any reg property for quite some time, so we don't need the size-cells property. Remove it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Remove useless AHCI propertiesMaxime Ripard1-2/+0
The SATA controller never have any children nodes, so we don't need the address and size cells properties. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Fix AHCI reset-names propertyMaxime Ripard1-1/+1
The AHCI node was introduced with a typo in the reset-names property that got written resets-name instead. This was working because the reset is optional for that driver, and the controller was put out of reset by the bootloader. Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: sunxi: dts: Split USB PHY cells into an arrayMaxime Ripard3-3/+3
Even though it doesn't make any difference at the binary level, the reg property is an array of cells, and should be represented as such. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: tbs-a711: Fix typo in regulatorsMaxime Ripard1-2/+2
The regulator properties suffix is -supply, yet a _supply slipped in. This was working because the regulator framework will provide a dummy regulator when none is provided in the device tree, and the regulator itself was always enabled. Fixes: 90c5d7cdae64 ("ARM: dts: sun8i: a711: Add regulator support") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Fix the TCON output clockMaxime Ripard8-0/+11
Even though we shouldn't really have any external user of the clock provided by the TCON, if clock-output-names is set, then #clock-cells must be there as well. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: sunxi: Fix the USB PHY VBUS detect GPIO propertiesMaxime Ripard19-19/+19
While the USB PHY Device Tree mandates that the name of the VBUS detect pin should be usb0_vbus_det-gpios, a significant number of device tree use usb0_vbus_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: sunxi: Fix the USB PHY ID detect GPIO propertiesMaxime Ripard39-39/+39
While the USB PHY Device Tree mandates that the name of the ID detect pin should be usb0_id_det-gpios, a significant number of device tree use usb0_id_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Switch to new GPIOs properties for i2c-gpioMaxime Ripard2-5/+5
The i2c-gpio driver uses named gpios now and the array of GPIOs is deprecated. Switch to the new binding. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Fix GIC compatibleMaxime Ripard6-6/+6
As can be shown by the YAML schema now, the combination of GIC compatibles we were using has never been an option. Switch to the gic-400 variant, which is the more correct option. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun5i: lichee-pi one: Remove stale pinctrl-names entryMaxime Ripard1-1/+0
Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: optimus: Fix fixed-regulatorsMaxime Ripard1-2/+2
Commit 1848f3f44444 ("ARM: dts: sun9i: Remove GPIO pinctrl nodes to avoid warnings") was wrong on the optimus, and instead of droping the pinctrl-names property, it dropped the regulator-name one. Obviously, that wasn't what was intended. Reinstate regulator-name and drop pinctrl-names. Fixes: 1848f3f44444 ("ARM: dts: sun9i: Remove GPIO pinctrl nodes to avoid warnings") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a23/a33: Add R_I2C ControllerMaxime Ripard1-0/+20
The A23 and A33 both have an I2C controller in the ARISC domain, that share the same pins with the RSB bus. Even if it's an unusual configuration, that device can be used to drive the PMIC, so let's use it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a33: Add default address and size cells to the DSI nodeMaxime Ripard1-0/+2
The DSI bindings require that an address cell size of 1, and a size cell of 0. Instead of duplicating it in each and every board DTS file, let's put it in the DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: Add missing unit addressMaxime Ripard1-1/+1
The soc node in the A80 DTSI has a ranges property, but no matching unit address, which results in a DTC warning. Add the unit address to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: Fix Display Engine DTC warningsMaxime Ripard2-64/+15
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Fix Display Engine DTC warningsMaxime Ripard1-4/+1
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a83t: Fix Display Engine DTC warningsMaxime Ripard2-4/+1
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: v3s: Fix Display Engine DTC warningsMaxime Ripard1-8/+2
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a23/a33: Fix Display Engine DTC warningsMaxime Ripard6-63/+29
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun6i: Fix Display Engine DTC warningsMaxime Ripard2-20/+4
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun5i: Fix Display Engine DTC warningsMaxime Ripard2-11/+2
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTCMaxime Ripard1-20/+5
Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a83t: Add cross links for the mixersMaxime Ripard1-2/+28
Unlike what the binding for multiple pipeline documents, the A83t doesn't have the cross links between the TCON and the mixers. Let's add them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun7i: olimex-lime2: Add regulators for GPIO banksPriit Laes1-0/+6
Make sure that A20 Olimex Lime2 pin bank regulators are properly represented. While pin banks A, B and F are connected to 3.3V static regulator, pin banks E and G tied with LDO3 and LDO4 regulators with 2.8V reference. Signed-off-by: Priit Laes <priit.laes@paf.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun7i: add /omit-if-no-ref/ tags to pin group nodesMans Rullgard1-0/+42
Since only one alternative at a time is used, and some functions may not be used at all, this cuts down the size of the board dtb files a bit. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun7i: add pinctrl for EMAC in PH bankMans Rullgard1-0/+10
This adds pinctrl settings the EMAC using pins in the PH block. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun7i: add pinctrl for CAN in PA bankMans Rullgard1-0/+6
This adds pinctrl settings for the CAN controller using pins PA16 and PA17. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun7i: add pinctrl for missing uart mux optionsMans Rullgard1-0/+54
This adds pinctrl settings for various missing uart options. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: h3: Refactor the pinctrl node namesMaxime Ripard17-43/+43
The H3 and H5 have never been converted to the new convention we want to have for the pinctrl nodes. Convert them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entryMaxime Ripard4-8/+0
Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: exynos: Fix spelling mistake of EXYNOS5420Benjamin Drung1-1/+1
The SoC name EXYNOS5420 was misspelled. Signed-off-by: Benjamin Drung <bdrung@posteo.de> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-03-25Merge tag 'imx-fixes-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesArnd Bergmann4-6/+7
i.MX fixes for 5.1: - Correct phy mode setting of imx6dl-yapp4 board to fix a problem caused by commit 5ecdd77c61c8 ("net: dsa: qca8k: disable delay for RGMII mode"). - Add a missing of_node_put call to fix leaked reference detected by coccinelle in imx51 machine code. - Fix imx6q cpuidle driver bug which causes that CPU might not wake up at expected time. - Increase reset duration of Ethernet phy Micrel KSZ9031RNX to fix transmission timeouts error seen on imx6qdl-phytec-pfla02 board. - Correct SPDX License Identifier style for imx6ull-pinfunc-snvs.h. - Fix 'bus-witdh' typos in imx6qdl-icore-rqs.dtsi. - Correct pseudo PHY address of switch device for imx6dl-yapp4 board. - Update PWM driver options in imx defconfig files due to the change on driver part. * tag 'imx-fixes-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx_v4_v5_defconfig: enable PWM driver ARM: imx_v6_v7_defconfig: continue compiling the pwm driver ARM: dts: imx6dl-yapp4: Use correct pseudo PHY address for the switch ARM: dts: imx6qdl: Fix typo in imx6qdl-icore-rqs.dtsi ARM: dts: imx6ull: Use the correct style for SPDX License Identifier ARM: dts: pfla02: increase phy reset duration ARM: imx6q: cpuidle: fix bug that CPU might not wake up at expected time ARM: imx51: fix a leaked reference by adding missing of_node_put ARM: dts: imx6dl-yapp4: Use rgmii-id phy mode on the cpu port
2019-03-25Merge tag 'arm-soc/for-5.1/devicetree-fixes' of https://github.com/Broadcom/stblinux into arm/fixesArnd Bergmann1-1/+1
This pull request contains Broadcom ARM-based SoCs Device Tree fixes for 5.1, please pull the following: - Helen fixes the HDMI hot-pug detect GPIO polarity for the Rasperry Pi model B revision 2 * tag 'arm-soc/for-5.1/devicetree-fixes' of https://github.com/Broadcom/stblinux: ARM: dts: bcm283x: Fix hdmi hpd gpio pull
2019-03-25ARM: dts: nomadik: Fix polarity of SPI CSLinus Walleij1-4/+5
The SPI DT bindings are for historical reasons a pitfall, the ability to flag a GPIO line as active high/low with the second cell flags was introduced later so the SPI subsystem will only accept the bool flag spi-cs-high to indicate that the line is active high. It worked by mistake, but the mistake was corrected in another commit. The comment in the DTS file was also misleading: this CS is indeed active high. Fixes: cffbb02dafa3 ("ARM: dts: nomadik: Augment NHK15 panel setting") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-03-25ARM: dts: rockchip: Remove #address/#size-cells from rk3288-veyron gpio-keysDouglas Anderson1-2/+0
They are pointless. As dtc points out: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Let's remove them. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-25ARM: dts: rockchip: Remove #address/#size-cells from rk3288 mipi_dsiDouglas Anderson1-2/+0
They are pointless. As dtc points out: Warning (avoid_unnecessary_addr_size): /mipi@ff960000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Let's remove them. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-25ARM: dts: rockchip: Fix gpu opp node names for rk3288Douglas Anderson1-6/+6
The device tree compiler yells like this: Warning (unit_address_vs_reg): /gpu-opp-table/opp@100000000: node has a unit name, but no reg property Let's match the cpu opp node names and use a dash. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-25ARM: dts: rockchip: Add vdd_logic to rk3288-veyronDouglas Anderson1-0/+17
The vdd_logic rail controls the voltage supplied to misc logic on rk3288, including the voltage supplied to the memory controller. The vcc logic is implemented by a PWM regulator. Right now there are no consumers of vdd_logic on veyron but if anyone ever wants to try to add DDR Freq they'd need it. Note that in the downstream Chrome OS kernel the PWM regulator has a voltage table with these points: 1350000 0% 1300000 10% 1250000 20% 1200000 31% 1150000 41% 1125000 46% 1100000 52% 1050000 62% 1000000 72% 950000 83% The DDR Freq driver in the downstream kernel only uses some of those points, namely: DDR3: 1200000, 1150000, 1100000, 1050000 LPDDR: 1150000, 1100000, 1050000 When adapting the downstream kernel to upstream I have opted to switch to using the "continuous" mode of the PWM regulator driver. This was the only way I could get the upstream driver to achieve _exactly_ the same voltages as the downstream driver could. Specifically note that the old driver in downstream Chrome OS 3.14 _didn't_ have the DIV_ROUND_CLOSEST_ULL() in the Rockchip PLL driver. That means if I use the same (downstream) table I might end up with a duty cycle that's 1 larger than was used downstream, leading to a slightly different voltage. Due to the way the rounding worked I couldn't even just adjust the "percent" by 1 for a given voltage level--certain duty cycles just aren't achievable with the upstream math for voltage tables. Using continuous mode you can achieve the exact same duty cycle by simply adjusting the voltage you use by a tad bit. The voltages that are equivalent to the ones used in the downstream kernel's table are: 1350000, 1304472, 1255691, 1200407, 1154878, 1128862, 1099593, 1050813, 1005285, 950000 Note that the top/bottom voltage is exactly the same just due to the way that continuous mode is calculated and the fact that I used those as anchors. I didn't make any attempt to do the resistor math (as was done on rk3399-gru). If anyone ever gets DDRFreq working on veyron upstream they should thus adjust the voltage specified in the DDRFreq operating points slightly (as per the above) to obtain the existing/tested values. AKA you'd use: DDR3: 1200407, 1154878, 1099593, 1050813 LPDDR: 1154878, 1099593, 1050813 A few other notes: - The "period" here (1994) is different than the "period" downstream (2000) for similar reasons: there's a DIV_ROUND_CLOSEST_ULL() that wasn't downstream. With 1994 upstream comes up with the same value (0x94) to program into the hardware that downstream put there. As far as I can tell 0x94 actually means 1993.27. - The duty cycle unit of 0x94 was picked by just matching the period which nicely allows us to insert 0x7b as that value to program into the hardware for 950mV. The 0x7b was found by observing what the downstream kernel calculated (not that the system can actually run with vdd_log at 950 mV). - The downstream kernel can also be seen to program a different value into the CTRL field. Upstream achieves 0x0b and downstream 0x1b. This is because the upstream commit bc834d7b07b4 ("pwm: rockchip: Move the configuration of polarity") fixed a bug by adding "ctrl &= ~PWM_POLARITY_MASK". Downstream accidentally left bit 4 set. Luckily this bit doesn't matter--it's only used when the PWM goes inactive (AKA if it's in oneshot mode or is disabled) and we don't do that for the PWM regulator. I measured the voltage of vdd_log while adjusting it and found that with the upstream kernel voltage difference between requested and actual was 9.2 mV at 950 mV and 13.4 mV at 1350 mV with in-between voltages consistently showing ~1% error. This error is likely expected as voltage can be seen to sag a bit when more load is put on the rail. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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