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2013-01-22ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructuresBarry Song1-0/+3
this patch adds tick timer, smp entries and generic DT machine for SiRFmarco dual-core SMP chips. with the added marco, we change the defconfig, using the same defconfig, we get a zImage which can work on both prima2 and marco. Signed-off-by: Barry Song <Baohua.Song@csr.com> Cc: Mark Rutland <mark.rutland@arm.com>
2013-01-22ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marcoBarry Song1-1/+1
Marco timer has different timer IP with prima2, so rename the current timer to timer-prima2 so that we can add timer-marco. at the same time, if we don't find prima2 timer node in dt, don't panic the system as we will make prima2 and marco use same kernel image. Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-28ARM: SIRF: make sirf irqchip driver optional since new SoCs will have GICBarry Song1-1/+1
New MARCO and POLO SoC use GIC, so make irq.c optional and enable it only if we enable ARCH_PRIMA2 in Kconfig Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-28ARM: PRIMA2: use DT_MACHINE_START and convert to generic boardBarry Song1-1/+1
we will have SiRFMarco and SiRFPolo, all of them will be in the generic board. Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-24clk: prima2: move from arch/arm/mach to drivers/clkBarry Song1-1/+0
Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2011-09-21ARM: CSR: PM: add sleep entry for SiRFprimaIIRongjun Ying1-0/+1
This patch adds suspend-to-mem support for prima2. It will make prima2 enter DEEPSLEEP mode while accepting PM_SUSPEND_MEM command. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-09-11ARM: CSR: add rtc i/o bridge interface for SiRFprimaIIZhiwu Song1-0/+1
The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09ARM: CSR: initializing L2 cacheRongjun Ying1-0/+1
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09ARM: CSR: mapping early DEBUG_LL uartBarry Song1-0/+1
Signed-off-by: Barry Song <baohua.song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09ARM: CSR: Adding CSR SiRFprimaII board supportBinghua Duan1-0/+5
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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