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2012-08-28ARM: SIRF: make sirf irqchip driver optional since new SoCs will have GICBarry Song1-1/+1
New MARCO and POLO SoC use GIC, so make irq.c optional and enable it only if we enable ARCH_PRIMA2 in Kconfig Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-05-16ARM: PRIMA2: fix irq domain size and IRQ mask of internal interrupt controllerBarry Song1-2/+4
the old codes will cause 3.4 kernel warning as irq domain size is wrong: ------------[ cut here ]------------ WARNING: at kernel/irq/irqdomain.c:74 irq_domain_legacy_revmap+0x24/0x48() Modules linked in: [<c0013f50>] (unwind_backtrace+0x0/0xf8) from [<c001e7d8>] (warn_slowpath_common+0x54/0x64) [<c001e7d8>] (warn_slowpath_common+0x54/0x64) from [<c001e804>] (warn_slowpath_null+0x1c/0x24) [<c001e804>] (warn_slowpath_null+0x1c/0x24) from [<c005c3c4>] (irq_domain_legacy_revmap+0x24/0x48) [<c005c3c4>] (irq_domain_legacy_revmap+0x24/0x48) from [<c005c704>] (irq_create_mapping+0x20/0x120) [<c005c704>] (irq_create_mapping+0x20/0x120) from [<c005c880>] (irq_create_of_mapping+0x7c/0xf0) [<c005c880>] (irq_create_of_mapping+0x7c/0xf0) from [<c01a6c48>] (irq_of_parse_and_map+0x2c/0x34) [<c01a6c48>] (irq_of_parse_and_map+0x2c/0x34) from [<c01a6c68>] (of_irq_to_resource+0x18/0x74) [<c01a6c68>] (of_irq_to_resource+0x18/0x74) from [<c01a6ce8>] (of_irq_count+0x24/0x34) [<c01a6ce8>] (of_irq_count+0x24/0x34) from [<c01a7220>] (of_device_alloc+0x58/0x158) [<c01a7220>] (of_device_alloc+0x58/0x158) from [<c01a735c>] (of_platform_device_create_pdata+0x3c/0x80) [<c01a735c>] (of_platform_device_create_pdata+0x3c/0x80) from [<c01a7468>] (of_platform_bus_create+0xc8/0x190) [<c01a7468>] (of_platform_bus_create+0xc8/0x190) from [<c01a74cc>] (of_platform_bus_create+0x12c/0x190) ---[ end trace 1b75b31a2719ed32 ]--- Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-02-16irq_domain: Remove irq_domain_add_simple()Grant Likely1-1/+1
irq_domain_add_simple() was a stop-gap measure until complete irq_domain support was complete. This patch removes the irq_domain_add_simple() interface. This patch also drops the explicit irq_domain initialization performed by the mach-versatile code because the versatile interrupt controller already has irq_domain support built into it. This was a bug that was hanging around quietly for a while, but with the full irq_domain which actually verifies that irq_domain ranges are available it would cause the registration to fail and the system wouldn't boot. v4: Fixed number of irqs in mx5 gpio code v2: Updated to pass in host_data pointer on irq_domain allocation. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Milton Miller <miltonm@bga.com> Cc: Russell King <linux@arm.linux.org.uk> Tested-by: Olof Johansson <olof@lixom.net>
2011-09-21ARM: CSR: PM: save/restore irq status in suspend cycleBarry Song1-0/+40
SiRFprimaII will lose power in deepsleep mode except rtc, pmu and sdram self-refresh. So IRQ controller will lose status in suspend cyle. This patch saves irq mask/level registers while suspending and restore them while resuming. Signed-off-by: Barry Song <baohua.song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-09-11ARM: CSR: IRQ: add simple irq_domain so that hw irq can map to LinuxBarry Song1-0/+3
Signed-off-by: Barry Song <Baohua.Song@csr.com>
2011-09-11ARM: CSR: add missing sentinels to of_device_id tablesJamie Iles1-0/+1
The of_device_id tables used for matching should be terminated with empty sentinel values. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Barry Song <baohua.song@csr.com>
2011-07-09ARM: CSR: Adding CSR SiRFprimaII board supportBinghua Duan1-0/+71
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>