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Instead of using a simple variable access to get at the Tegra chip ID,
use a function so that we can run additional code. This can be used to
determine where the chip ID is being accessed without being available.
That in turn will be handy for resolving boot sequence dependencies in
order to convert more code to regular initcalls rather than a sequence
fixed by Tegra SoC setup code.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The CPUIdle function of Tegra124 is identical to Tegra114, so we share
the same driver with Tegra114.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra20 HW appears to have a bug such that PCIe device interrupts,
whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To
work around this, simply disable LP2 if any PCIe devices with interrupts
are present. Detect this via the IRQ domain map operation. This is
slightly over-conservative; if a device with an interrupt is present but
the driver does not actually use them, LP2 will still be disabled.
However, this is a reasonable trade-off which enables a simpler
workaround.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Clean up the Tegra CPUidle init function by using IS_ENABLED for multi
SoCs management in the init function.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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One of the state of CPUidle on Tegra can power gate the CPU and the
vdd_cpu rail. But it depends on some configurations from DT and a common
hook function for different Tegra SoCs to power gate the CPU rail. And
these stuffs are initialized after common Tegra suspend init function. So
we move the CPUidle init behind the suspend init function. And making the
CPUidle driver more generic.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The Tegra CPU idle LP3 state is doing ARM WFI only. So it's same with
the common ARM_CPUIDLE_WFI_STATE. Using it to replace LP3 now.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This should make it easier to delete or move <mach/*.h>; something that
is useful for single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This particular code had no effect on WFI execution. It only
asserts/de-asserts signal to tegra "legacy" CPU idle stats
monitor, which we are no longer using (cpufreq is based on
kernel s/w idle stats instead).
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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CPUidle driver for tegra. In this version only LP3 (clockgating) is supported.
Based on work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Thierry Reding
Joseph Lo
Stephen Warren
Prashant Gaikwad
Peter De Schrijver