linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2017-10-20	arm64: dts: fix unit-address leading 0s	Rob Herring	1	-16/+16
	Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '.dts' Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-09-14	arm64: dts: Fix broken architected timer interrupt trigger	Marc Zyngier	1	-4/+4
	The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-18	arm64: dts: Add Cavium ThunderX specific PMU	Jan Glauber	1	-0/+5
	Add a compatible string for the Cavium ThunderX PMU. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2015-07-08	GICv3: Add ITS entry to THUNDER dts	Tirumalesh Chalamarla	1	-0/+9
	The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on Thunder SoCs by adding an entry to DT. Signed-off-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-10-21	dts, arm64: Move dts files to vendor subdirs	Robert Richter	1	-0/+401
	Moving dts files to vendor subdirs. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Robert Richter <rrichter@cavium.com>