linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2018-06-19	arm64: dts: freescale: Update to use SPDX identifiers	Li Yang	1	-37/+1
	Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-12-26	arm64: dts: ls1088a: Add USB support	yinbo.zhu	1	-0/+8
	Add USB support on ls1088ardb Signed-off-by: yinbo zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-08-14	arm64: dts: ls1088: Correction in Board name from "L1088A" to "LS1088A"	Ashish Kumar	1	-1/+1
	Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15	arm64: dts: Add flash node for ls1088a qds and rdb	Prabhakar Kushwaha	1	-0/+16
	LS1088AQDS consist of NOR, NAND and FPGA connected over IFC LS1088ARDB consist of NAND and FPGA connected over IFC. So add flash information in ifc node of device tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15	arm64: dts: ls1088a: add esdhc node	Yangbo Lu	1	-0/+4
	Add esdhc node for ls1088a and enable it on both RDB and QDS boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-29	arm64: dts: Add support for FSL's LS1088A SoC	Harninder Rai	1	-0/+107
	LS1088A contains eight ARM v8 CortexA53 processor cores with 32 KB L1-D cache and 32 KB L1-I cache Features summary Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Arranged as two clusters of four cores sharing a 1 MB L2 cache - Speed Up to 1.5 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 700 MHz One 64-bit DDR4 SDRAM memory controller with ECC Data path acceleration architecture 2.0 (DPAA2) Three PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Three high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1088A SoC family: - fsl-ls1088a.dtsi: DTS-Include file for NXP LS1088A SoC. - fsl-ls1088a-qds.dts: DTS file for NXP LS1088A QDS board. - fsl-ls1088a-rdb.dts: DTS file for NXP LS1088A RDB board Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>` Signed-off-by: Shawn Guo <shawnguo@kernel.org>