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2022-04-26arm64: dts: mediatek: align thermal zone node names with dtschemaKrzysztof Kozlowski2-2/+2
Align the name of thermal zone node to dtschema to fix warnings like: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml: thermal-zones: 'cpu_thermal' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20210820081616.83674-2-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-26arm64: dts: mediatek: align operating-points table name with dtschemaKrzysztof Kozlowski3-5/+5
Align the name of operating-points node to dtschema to fix warnings like: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml: opp_table0: $nodename:0: 'opp_table0' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20210820081616.83674-1-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-26arm64: dts: mediatek: mt8183: align Google CROS EC PWM node name with dtschemaKrzysztof Kozlowski1-1/+1
dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220214081916.162014-3-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-25arm64: tegra: Update PWM fan node nameJon Hunter4-4/+4
According to the device-tree binding document for PWM fans [0], the PWM fan node name should be 'pwm-fan'. Update the PWM fan node name to align with this. [0] Documentation/devicetree/bindings/hwmon/pwm-fan.txt Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-25arm64: tegra: Add node for Tegra234 CCPLEX clusterSumit Gupta1-0/+7
Adding CCPLEX cluster node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for CPU frequency requests. These registers are memory mapped to the CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers is required only for CPU frequency info. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-25arm64: dts: fvp: Align virtio device node names with dtschemaSudeep Holla3-5/+5
Align the virtio mmio device tree node names with the schema to avoid any schema warnings. Link: https://lore.kernel.org/r/20220425135524.1077986-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: fvp: Add virtio-rng supportDiego Sueiro3-2/+10
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17, so add the devicetree node to support it. It is disabled by default to avoid any issues with models that doesn't support it. Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com Signed-off-by: Diego Sueiro <diego.sueiro@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: Add Arm corstone1000 platform supportRui Miguel Silva4-0/+248
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25Revert "arm64: dts: tegra: Fix boolean properties with values"Arnd Bergmann8-27/+27
This reverts commit 1a67653de0dd, which caused a boot regression. The behavior of the "drive-push-pull" in the kernel does not match what the binding document describes. Revert Rob's patch to make the DT match the kernel again, rather than the binding. Link: https://lore.kernel.org/lkml/YlVAy95eF%2F9b1nmu@orome/ Reported-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-24arm64: dts: imx8mn-evk: Add UART3 supportFabio Estevam1-0/+18
UART3 pins are available in the J1003 connector. Add support for it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-24arm64: dts: imx8mn-ddr4-evk: Describe the 32.768 kHz PMIC clockFabio Estevam1-0/+4
The ROHM BD71847 PMIC has a 32.768 kHz clock. Describe the PMIC clock to fix the following boot errors: bd718xx-clk bd71847-clk.1.auto: No parent clk found bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22 Based on the same fix done for imx8mm-evk as per commit a6a355ede574 ("arm64: dts: imx8mm-evk: Add 32.768 kHz clock to PMIC") Fixes: 3e44dd09736d ("arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support") Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-24arm64: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo boardMarek Vasut2-0/+322
Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo. The board is a compatible replacement for i.MX53 M53Menlo and features USB, multiple UARTs, ethernet, LEDs, SD and eMMC. Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Francesco Dolcini <francesco.dolcini@toradex.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-04-23arm64: dts: qcom: sc7280-idp: Enable GPI DMAsVinod Koul1-0/+8
Some versions of the firmware for the sc7280-idp board FIFO mode disabled and must thus use GPI DMA. Enable gpi_dma0 and gpi_dma1 to allow this. Co-developed-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220421115526.1828659-3-vkoul@kernel.org
2022-04-23arm64: dts: qcom: sc7280: Add GENI I2C/SPI DMA channelsVinod Koul1-0/+97
The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Co-developed-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220421115526.1828659-2-vkoul@kernel.org
2022-04-23arm64: dts: qcom: sc7280: Add GPI DMAenginesVinod Koul1-0/+44
The Qualcomm SC7280 has two GPI DMAengines, add definitions for these. Co-developed-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220421115526.1828659-1-vkoul@kernel.org
2022-04-23arm64: dts: qcom: sm8450: Fix qmp phy node (use phy@ instead of lanes@)Bhupesh Sharma1-2/+2
Fix the following 'make dtbs_check' warning(s) by using phy@ instead of lanes@: arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: phy@1c0f000: 'lanes@1c0e000' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220418205509.1102109-5-bhupesh.sharma@linaro.org
2022-04-23arm64: dts: qcom: db845c: Add support for MCP2517FDVinod Koul1-0/+32
Add support for onboard MCP2517FD SPI CAN transceiver attached to SPI0 of RB3. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220421073438.1824061-1-vkoul@kernel.org
2022-04-23arm64: dts: qcom: qrb5165-rb5: Fix can-clock node nameVinod Koul1-1/+1
Per DT spec node names should not have underscores (_) in them, so change can_clock to can-clock. Fixes: 5c44c564e449 ("arm64: dts: qcom: qrb5165-rb5: Add support for MCP2518FD") Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220421073502.1824089-1-vkoul@kernel.org
2022-04-22Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netPaolo Abeni14-40/+40
drivers/net/ethernet/microchip/lan966x/lan966x_main.c d08ed852560e ("net: lan966x: Make sure to release ptp interrupt") c8349639324a ("net: lan966x: Add FDMA functionality") Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-04-21arm64: dts: qcom: sc7280: Set the default dr_mode for usb2Souradeep Chowdhury1-1/+1
Set the default dr_mode for usb2 node to "otg" to enable role-switch for EUD(Embedded USB Debugger) connector node. Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Link: https://lore.kernel.org/r/451392a942f90aa9805b00afad7dff894604d189.1649235218.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-04-21arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connectorSouradeep Chowdhury1-0/+36
Add the Embedded USB Debugger(EUD) device tree node. The node contains EUD base register region and EUD mode manager register regions along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. Also add the role-switch property to dwc3 node. Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Link: https://lore.kernel.org/r/17a6127d1f0e4e3bac023dacf60a9ba93c1e21d1.1649235218.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-04-21Merge tag 'samsung-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann4-19/+10
Samsung DTS ARM64 changes for v5.19 1. Cleanup: move aliases of board-related features to board in Exynos850. 2. Add specific compatibles to Multi Core Timer to allow stricter DT schema matching. * tag 'samsung-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: tesla: add a specific compatible to MCT on FSD arm64: dts: exynos: add a specific compatible to MCT arm64: dts: exynos: move aliases to board in Exynos850 Link: https://lore.kernel.org/r/20220420072152.11696-3-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-19arm64: dts: qcom: sc7280: Add SAR sensors to herobrine crdMatthias Kaehlcke1-0/+12
Enable the two SAR sensors of the CRD based on herobrine. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220415172238.1.I671bdf40fdfce7a35f6349fca0dc56145d4210ee@changeid
2022-04-19arm64: dts: qcom: sm8250: camss: Add CCI definitionsBryan O'Donoghue1-0/+162
sm8250 has two CCI busses with two I2C busses apiece. Co-developed-by: Julian Grahsl <jgrahsl@snap.com> Signed-off-by: Julian Grahsl <jgrahsl@snap.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220415164655.1679628-4-bryan.odonoghue@linaro.org
2022-04-19arm64: dts: qcom: sm8250: camss: Add CAMSS block definitionBryan O'Donoghue1-0/+153
Adds a CAMSS definition block. Co-developed-by: Julian Grahsl <jgrahsl@snap.com> Signed-off-by: Julian Grahsl <jgrahsl@snap.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220415164655.1679628-3-bryan.odonoghue@linaro.org
2022-04-19arm64: dts: qcom: sm8250: Add camcc DT nodeBryan O'Donoghue1-0/+16
Add the camcc DT node for the Camera Clock Controller on sm8250. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220415164655.1679628-2-bryan.odonoghue@linaro.org
2022-04-19arm64: dts: qcom: sm8450-qrd: Enable spi and i2c nodesVinod Koul1-0/+24
Enable the i2c5, spi4, spi18 and spi19 nodes which were tested on qrd board along with related qup nodes and gpi_dma0 Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-8-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8450: Fix missing iommus for qup1Vinod Koul1-0/+3
qupv3_id_1 was missing iommus property which cause any dma transaction to fail and board crash. So add the missing iommus. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-7-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8450: Add qup nodes for qup2Vinod Koul1-0/+396
qup2 has 7 SEs, so add the SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-6-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8450: Add qup nodes for qup1Vinod Koul1-0/+359
qup1 has 7 SEs, I2C13 and I2C14 were already added so added the remaining SEs (i2c and spi) along with pinconf for these SEs Also add interconnect properties for I2C13 and I2C14 Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-5-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8450: Add qup nodes for qup0Vinod Koul1-0/+412
qup0 has 7 SEs, with SE7 as uart and already added, so add the remaining 6 SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-4-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8450: Fix missing iommus for qupVinod Koul1-0/+3
qupv3_id_0 was missing iommus property which cause any dma transaction to fail and board crash. So add the missing iommus. While at it also add interconnect nodes for qup Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-3-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8450: Add gpi_dma nodesVinod Koul1-0/+67
GPI DMA can be used for DMA operations for QUP devices, so add the three gpi_dma insances found in this SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-2-vkoul@kernel.org
2022-04-19arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1Bjorn Andersson1-0/+4
Some versions of the firmware for the SM8350 Hardware Development Kit (HDK) has FIFO mode disabled for i2c13 and must thus use GPI DMA. Enable &gpi_dma1 to allow this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220412215137.2385831-3-bjorn.andersson@linaro.org
2022-04-19arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channelsBjorn Andersson1-0/+108
The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220412215137.2385831-2-bjorn.andersson@linaro.org
2022-04-19arm64: dts: qcom: sm8350: Define GPI DMA enginesBjorn Andersson1-0/+73
The Qualcomm SM8350 has three GPI DMA engines, add definitions for these. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220412215137.2385831-1-bjorn.andersson@linaro.org
2022-04-19arm64: dts: qcom: sc7280: Add wakeup-source property for USB nodeSandeep Maheswaram1-0/+1
Adding wakeup-source property for USB controller in SC7280. This property is added to inform that the USB controller is wake up capable and to conditionally power down the phy during system suspend. Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1649704614-31518-7-git-send-email-quic_c_sanm@quicinc.com
2022-04-19arm64: dts: qcom: msm8996: override nodes by labelKrzysztof Kozlowski1-5/+3
Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220402192859.154977-2-krzysztof.kozlowski@linaro.org
2022-04-19arm64: dts: qcom: msm8994: override nodes by labelKrzysztof Kozlowski1-8/+6
Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220402192859.154977-1-krzysztof.kozlowski@linaro.org
2022-04-19arm64: dts: qcom: sdm845-xiaomi-beryllium: enable qcom wled backlight and link to panelJoel Selvaraj1-0/+12
Xiaomi Poco F1 uses the QCOM WLED driver for backlight control. Enable and link it to the panel to use it. Signed-off-by: Joel Selvaraj <jo@jsfamily.in> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/BY5PR02MB70092607CD7CDD8CF8BCD464D9E09@BY5PR02MB7009.namprd02.prod.outlook.com
2022-04-19arm64: dts: qcom: sdm845-xiaomi-beryllium: enable second wifi channelJoel Selvaraj1-0/+7
Like the c630, the Poco F1 is also capable of using both antenna channels for 2.4 and 5ghz wifi, however unlike the c630 only the first channel is used for bluetooth. Similar to Oneplus 6. Signed-off-by: Joel Selvaraj <jo@jsfamily.in> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/BY5PR02MB7009E2566F9000F338432761D91F9@BY5PR02MB7009.namprd02.prod.outlook.com
2022-04-19arm64: dts: qcom: sdm845-xiaomi-beryllium: fix typo in panel's vddio-supply propertyJoel Selvaraj1-1/+1
vddio is misspelled with a "0" instead of "o". Fix it. Signed-off-by: Joel Selvaraj <jo@jsfamily.in> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/BY5PR02MB7009901651E6A8D5ACB0425ED91F9@BY5PR02MB7009.namprd02.prod.outlook.com
2022-04-19arm64: dts: qcom: sdm845-xiaomi-beryllium: enable qcom ipa driverJoel Selvaraj1-0/+6
Enable Qualcomm IP Accelerator (IPA) driver for mobile data functionality which works by using ModemManager. Signed-off-by: Joel Selvaraj <jo@jsfamily.in> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/BY5PR02MB7009405D7C06C0B480974063D91F9@BY5PR02MB7009.namprd02.prod.outlook.com
2022-04-19arm64: dts: qcom: sdm845-xiaomi-beryllium: change firmware path and use mbn formatJoel Selvaraj1-4/+4
The "qcom/sdm845/" path conflicts with db845c's firmware that are present in the linux-firmware package. Xiaomi uses their own signed firmware for Poco F1 and can't use the db845c's firmware. So let's use "qcom/sdm845/beryllium/" to distinguish Poco F1's firmware files. For easier handling and packaging, the mdt+bXX files are squashed using Bjorn Andersson's pil-squasher tool from this link: https://github.com/andersson/pil-squasher Signed-off-by: Joel Selvaraj <jo@jsfamily.in> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/BY5PR02MB700966DEE6F6044EBEB5B892D91F9@BY5PR02MB7009.namprd02.prod.outlook.com
2022-04-19arm64: dts: qcom: do not use underscore in BCM node nameKrzysztof Kozlowski5-5/+5
Align BCM voter node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411085935.130072-3-krzysztof.kozlowski@linaro.org
2022-04-19arm64: dts: qcom: sm8450: Add thermal zonesVladimir Zapolskiy1-0/+843
Add thermal zones handled by tsens sensors. The definitions and the trip points were taken from the downstream dts. For the CPU core thermal sensors, the trip points were changed to follow the example of other Qualcomm platforms. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410234458.1739279-3-dmitry.baryshkov@linaro.org
2022-04-19arm64: dts: qcom: sm8450: Add thermal sensor controllersVladimir Zapolskiy1-0/+22
The change adds description of two thermal sensor controllers found on SM8450. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220410234458.1739279-2-dmitry.baryshkov@linaro.org
2022-04-19arm64: dts: qcom: msm8998: reserve potentially inaccessible clocksMichael Srba1-0/+15
With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration. Signed-off-by: Michael Srba <michael.srba@seznam.cz> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411072156.24451-6-michael.srba@seznam.cz
2022-04-19arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFSKrzysztof Kozlowski2-4/+4
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com
2022-04-19arm64: dts: renesas: r8a779f0: Add GPIO nodesGeert Uytterhoeven1-0/+60
Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that GPIO blocks 4-7 are not added, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be
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