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2022-09-17arm64: dts: imx8mm: Fix typo in license text for Engicam boardsJagan Teki3-3/+3
Fix the Amarula Solutions typo mistake in license text for Engicam i.MX8M boards add in below commits. commit <60ac35268f85b> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM") commit <aec8ad34f7f24> ("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit") commit <eefe06b295087> ("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8-ss-dma: add IPG clock for i2cPeng Fan1-8/+12
i.MX8 LPI2C requires both PER and IPG clock, so add the missed IPG clk. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-SFrieder Schrempf3-0/+707
This adds support for the Kontron Electronics SL i.MX8MM OSM-S SoM and the matching baseboard BL i.MX8MM OSM-S. The SoM hardware complies to the Open Standard Module (OSM) 1.0 specification, size S (https://sget.org/standards/osm). Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-kontron: Add SPI NOR partition layoutFrieder Schrempf1-0/+21
This is the layout used by the bootloader. Add it to the kernel devicetree to make the same layout available in Linux and have the devicetrees synced. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-kontron: Use voltage rail names from schematic for PMIC regulator-namesFrieder Schrempf1-11/+11
Improve the naming of the regulators to contain the voltage rail names from the schematic. Suggested-by: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-kontron: Remove low DDRC operating pointFrieder Schrempf1-4/+0
For some reason there is a problem with finding a DDR configuration that works on all operating points and all LPDDR4 types used on the SoM. Therefore the bootloader currently doesn't configure the lowest of the three operating points. Let's also skip this in the kernel devicetree to make sure it isn't used. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltageFrieder Schrempf2-2/+3
It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly. Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly. Reported-by: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-kontron: Adjust compatibles, file names and model stringsFrieder Schrempf3-6/+6
The official naming includes "SL" (SoM-Line) or "BL" (Board-Line). By updating we make sure, that we can maintain this more easily in future and make sure that the proper devicetree can be selected for the hardware. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: add VPU blk ctrl nodePeng Fan1-0/+17
Add i.MX8MP VPU blk ctrl node Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: add vpu pgc nodesPeng Fan1-0/+27
Add i.MX8MP PGC nodes for vpu, which are used to supply power for VPU. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp-verdin: add cpu-supplyMax Krummenacher1-1/+17
Add the cpu-supply property to all CPU nodes to enable the cpufreq driver. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-venice-gw7903: add digital I/O ctl gpiosTim Harvey1-1/+3
The GW7903-C revision introduced two additional GPIO's for controlling the digital I/O direction. Add them. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm/n-venice-gw7902: Remove invalid propertyFabio Estevam2-2/+0
The 'oscillator-frequency' property is not documented and it is not used anywhere. Remove it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: Add SoM compatible to i.MX8M Plus DHCOM PDK2Marek Vasut1-1/+2
Add SoM compatible string into i.MX8MP DHCOM PDK2 compatible strings. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: Drop Atheros PHY header from i.MX8M Plus DHCOM PDK2Marek Vasut1-1/+0
This PHY is not used on PDK2, the header was added due to copy-paste error, drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: Add HW variant details to i.MX8M Plus DHCOM PDK2Marek Vasut1-0/+5
Add information about which exact SoM variant is used on which PDK2 variant. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: mnt-reform2: don't use multiple blank linesMarcel Ziswiler1-1/+0
Avoid the following checkpatch warning: arch/arm/boot/dts/imx8mq-mnt-reform2.dts:213: check: Please don't use multiple blank lines Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp-verdin: don't use multiple blank linesMarcel Ziswiler1-1/+0
Avoid the following checkpatch warning: arch/arm/boot/dts/imx8mp-verdin.dtsi:281: check: Please don't use multiple blank lines Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mm-venice-gw72xx-0x: blank line at end of fileMarcel Ziswiler1-1/+0
Avoid the following checkpatch warning: Found possible blank line(s) at end of file 'arch/arm/boot/dts/imx8mm-venice-gw72xx-0x.dts' Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8ulp-evk: Add the fec supportWei Fang1-0/+57
Enable the fec on i.MX8ULP EVK board. Signed-off-by: Wei Fang <wei.fang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8ulp: Add the fec supportWei Fang1-0/+11
Add the fec support on i.MX8ULP platforms. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: add interconnect for hsio blk ctrlPeng Fan1-0/+5
Add interconnect property for hsio blk ctrl Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17arm64: dts: imx8mp: add interconnects for media blk ctrlPeng Fan1-0/+13
Add interconnect property for media blk ctrl Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-16arm64: dts: qcom: sc7280: Add required-opps for USBRajendra Nayak1-0/+3
USB has a requirement to put a performance state vote on 'cx' while active. Use 'required-opps' to pass this information from device tree, and since all the GDSCs in GCC (including USB) are sub-domains of cx, we also add cx as a power-domain for GCC. Now when any of the consumers of the GDSCs (in this case USB) votes on a perforamance state, genpd framework can identify that the GDSC itself does not support a performance state and it then propogates the vote to the parent, which in this case is cx. This change would also mean that any GDSC in GCC thats left enabled during low power state (perhaps because its marked with a ALWAYS_ON flag) can prevent the system from entering low power since that would prevent cx from transitioning to low power. Ideally any consumers that would need to have their devices (partially) powered to support wakeups should look at making the resp. GDSCs transtion to a Retention (PWRSTS_RET) state instead of leaving them ALWAYS_ON. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220916103124.30581-1-quic_rjendra@quicinc.com
2022-09-16arm64: dts: qcom: sm8350: fix UFS PHY serdes sizeJohan Hovold1-1/+1
The size of the UFS PHY serdes register region is 0x1c4 and the corresponding 'reg' property should specifically not include the adjacent regions that are defined in the child node (e.g. tx and rx). Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220916093603.24263-1-johan+linaro@kernel.org
2022-09-16arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise EditionTianling Shen2-0/+30
The only diffrence against the standrard edition is that the enterprise one has a built-in EEPROM chip which stores a globally unique MAC address. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20220915022511.4267-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-16arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30Quentin Schulz1-0/+22
The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are 2-channel I2S/PCM controllers handled by the same controller driver, and i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller driver. This adds the device tree node required to enable I2S0 on PX30. This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX (rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board. Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20220916091746.35108-1-foss+kernel@0leil.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-15Merge tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dtArnd Bergmann2-0/+131
This pull request contains Broadcom ARM64-based SoC changes for 6.1, please pull the following: - Rafal adds the BCM4908 LED controller node and describes all 32 LED pins, he also adds support for the Asus GC-AC5300 LEDs * tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs arm64: dts: broadcom: bcm4908: add LEDs controller block arm64: dts: broadcom: bcm4908: add remaining LED pins Link: https://lore.kernel.org/r/20220915023044.2350782-3-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15Merge tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux into arm/dtArnd Bergmann10-10/+39
This pull request contains Broadcom ARM-based SoC Device Tree updates for 6.1, please pull the following: - Rafal improves the BCM5301X PCIe DT nodes schema validation by flagging the PCIe controller with a missing "device_type" property - William merges BCM4908 within BCMBCA since this chip is part of the Broadcom Broadband Carrier Access group and follows the architecture of those chips * tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux: arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA arm64: dts: Add BCM4908 generic board dts arm64: dts: Move BCM4908 dts to bcmbca folder arm64: dts: bcmbca: update BCM4908 board dts files dt-bindings: arm64: bcmbca: Update BCM4908 description dt-bindings: arm64: bcmbca: Merge BCM4908 into BCMBCA ARM: dts: BCM5301X: Add basic PCI controller properties Link: https://lore.kernel.org/r/20220915023044.2350782-2-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15arm64: tegra: Add GPCDMA support for Tegra I2CAkhil R3-0/+96
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add iommus for HDA on Tegra234Mohan Kumar1-0/+1
Add the iommus property to the HDA node on Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Enable HDA node for Jetson AGX OrinMohan Kumar1-0/+1
Enable HDA node for the Jetson AGX Orin platform. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add context isolation domains on Tegra234Mikko Perttunen1-0/+18
Add Host1x context isolation domains on Tegra234. On Tegra234 we have two IOMMUs that are connected to Host1x-channel programmed engines, so we have to include domains for each of them. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Fixup iommu-map property formattingThierry Reding2-18/+16
Make sure that each phandle-array is enclosed in a set of angular brackets and properly indent each entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: dts: tegra: smaug: Add Wi-Fi nodeDiogo Ivo1-0/+19
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module. Add a DT node for its Wi-Fi functionality. Tested on Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: dts: tegra: smaug: Add Bluetooth nodeDiogo Ivo1-0/+17
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module. Add a DT node for its BT functionality. Tested on Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Enable MGBE on Jetson AGX Orin Developer KitThierry Reding1-0/+21
A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet port on the Jetson AGX Orin Developer Kit. Enable it. Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add MGBE nodes on Tegra234Thierry Reding1-0/+136
Add device tree nodes for the four instances of the Multi-Gigabit Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Fix up compatible for Tegra234 GPCDMAThierry Reding1-1/+0
There is no need to list the Tegra194-specific compatible for Tegra234 because the backwards-compatibility goes back all the way to Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Enable PCIe slots in P3737-0000 boardVidya Sagar1-0/+51
Enable PCIe controller nodes to enable respective PCIe slots on P3737-0000 board. Following is the ownership of slots by different PCIe controllers. Controller-1 : On-board Broadcom WiFi controller Controller-4 : M.2 Key-M slot Controller-5 : CEM form-factor x8 slot Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DTVidya Sagar1-0/+927
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree. The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us) NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us) respectively. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add regulators required for PCIeVidya Sagar1-0/+36
Add regulator supplies required for PCIe functionality. The supplies include 1.8V, 3.3V and 12V. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: dts: qcom: sm8450: fix UFS PHY serdes sizeJohan Hovold1-1/+1
The size of the UFS PHY serdes register region is 0x1c4 and the corresponding 'reg' property should specifically not include the adjacent regions that are defined in the child node (e.g. tx and rx). Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220915143431.19842-2-johan+linaro@kernel.org
2022-09-15arm64: dts: mediatek: mt6795: Add CPUX system timer nodeAngeloGioacchino Del Regno1-0/+8
Add a node for mt6795-systimer: this is necessary to start the System Timer(s) for all cores, finally making CNTVCT_EL0 usable. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220729093536.27623-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-09-15arm64: dts: qcom: ipq8074: fix PCIe PHY serdes sizeJohan Hovold1-2/+2
The size of the PCIe PHY serdes register region is 0x1c4 and the corresponding 'reg' property should specifically not include the adjacent regions that are defined in the child node (e.g. tx and rx). Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220915143431.19842-1-johan+linaro@kernel.org
2022-09-15Merge tag 'imx-fixes-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesArnd Bergmann8-18/+30
i.MX fixes for 6.0, 2nd round: - A couple of TQMa8MPQL device tree fixes from Alexander Stein on button GPIOs and PCF85063 RTC alarm pinctrl. - Include phy-imx8-pcie.h header in tqma8mqml-mba8mx device tree to fix build errors when this SoM dtsi is included on customer carrier boards. - Remove GPU power domain reset from i.MX8MN device tree to fix a sporadical hang seen with GPUMIX powering up. - Correct CPLD_Dn GPIO label mapping for Toradex Verdin based Menlo board. - Add ARCH_NXP back to defconfig, which was dropped accidentally by commit 566e373fe047 ("arm64: Kconfig.platforms: Group NXP platforms together"). - Add missing #reset-cells for i.MX8ULP PCC clock controllers. - Update PMIC voltages for imx8mm-verdin board to fix an issue with one Toradex SKU that uses a consumer-grade chip that is capable of going up to 1.8GHz at 1.00V. - A series of imx8mp-venice-gw74xx device tree changes from Tim Harvey to fix things on CAN STBY polarity, KSZ9477 CPU uplink port and phy-mode. * tag 'imx-fixes-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mp-venice-gw74xx: fix port/phy validation arm64: dts: imx8mp-venice-gw74xx: fix ksz9477 cpu port arm64: dts: imx8mp-venice-gw74xx: fix CAN STBY polarity arm64: dts: tqma8mqml: Include phy-imx8-pcie.h header arm64: defconfig: enable ARCH_NXP arm64: dts: imx8mp-tqma8mpql-mba8mpxl: add missing pinctrl for RTC alarm arm64: dts: imx8mm-verdin: extend pmic voltages arm64: dts: imx8ulp: add #reset-cells for pcc arm64: dts: tqma8mpxl-ba8mpxl: Fix button GPIOs arm64: dts: imx8mn: remove GPU power domain reset arm64: dts: imx8mm: Reverse CPLD_Dn GPIO label mapping on MX8Menlo Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pcMarkus Reichl1-2/+4
Add avdd-0v9-supply and avdd-1v8-supply to hdmi node for rk3399-roc-pc to silence dmesg warning and match the name of the 1v8 supply to the circuit sheet. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/20220915111138.1108-1-m.reichl@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-15arm64: dts: rockchip: Support gru-scarlet sku{2,4} variantsBrian Norris1-1/+13
The Gru-Scarlet family includes a variety of SKU identifiers, using parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few different manufacturer names) also use the Innolux display. Without this, a SKU2 device may non-deterministically (depending on the matching order of DTBs and bootloader behavior) select either one of the INX DTBs (rk3399-gru-scarlet-dumo.dtb or rk3399-gru-scarlet-inx.dtb) or the KingDisplay DTB (rk3399-gru-scarlet-kd.dtb), to ill effect. For reference, the original vendor tree source: CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc Signed-off-by: Brian Norris <briannorris@chromium.org> Link: https://lore.kernel.org/r/20220817123350.2.I5f4fd0808a927b08e267c189712fb4a85931fd3b@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-14arm64: dts: qcom: sa8295p-adp: add missing gpio-ranges in PMIC GPIOsKrzysztof Kozlowski1-0/+4
The Qualcomm PMIC GPIO bindings require gpio-ranges property: qcom/sa8295p-adp.dtb: pmic@8: gpio@c000: 'gpio-ranges' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908081050.29751-5-krzysztof.kozlowski@linaro.org
2022-09-14arm64: dts: qcom: sa8295p-adp: add fallback compatible to PMIC GPIOsKrzysztof Kozlowski1-4/+4
Bindings require all PMIC GPIO nodes to have two compatibles - specific followed by SPMI or SSBI fallback: qcom/sa8295p-adp.dtb: pmic@8: gpio@c000:compatible: ['qcom,pm8150-gpio'] is too short Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908081050.29751-4-krzysztof.kozlowski@linaro.org
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