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2022-02-24Merge tag 'imx-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesArnd Bergmann2-2/+1
i.MX fixes for 5.17, round 2: - Drop reset signal from i.MX8MM vpumix power domain to fix a system hang. - Fix a dtbs_check warning caused by #thermal-sensor-cells in i.MX8ULP device tree. - Fix a clock disabling imbalance in gpcv2 driver. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-24Merge tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixesArnd Bergmann9-18/+42
Fix the display-port-sound on Gru devices, DDR voltage on the Quartz-A board, fix emmc signal-integrity and usb OTG mode on rk3399-puma as well as a number of dtschema fixes to make the reduce the number of errors. * tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: fix a typo on rk3288 crypto-controller ARM: dts: rockchip: reorder rk322x hmdi clocks arm64: dts: rockchip: reorder rk3399 hdmi clocks arm64: dts: rockchip: align pl330 node name with dtschema arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage arm64: dts: rockchip: Switch RK3399-Gru DP to SPDIF output arm64: dts: rockchip: fix rk3399-puma-haikou USB OTG mode arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568 arm64: dts: rockchip: fix dma-controller node names on rk356x Link: https://lore.kernel.org/r/1973741.CViHJPHrxy@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-24arm64: dts: qcom: sdm632: Add device tree for Fairphone 3Luca Weiss2-0/+184
Add device tree for the Fairphone 3 smartphone which is based on Snapdragon 632 (sdm632). Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-11-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: Add SDM632 device treeVladimir Lypak1-0/+81
Snapdragon 632 is based on msm8953 with some minor differences, mostly in the CPUs. SDM632 is using Kryo 250 instead of ARM Cortex A53 and has some differences in the thermal zones, mainly there being only one thermal zones for the first 4 cores (efficiency cores) but keeps one thermal zone per core for the remaining 4 cores (performance cores). Co-developed-by: Gabriel David <ultracoolguy@disroot.org> Signed-off-by: Gabriel David <ultracoolguy@disroot.org> Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-9-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: Add PM8953 PMICVladimir Lypak1-0/+90
Add a base DT for PM8953 PMIC, commonly used with MSM8953. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rayyan Ansari <rayyan@ansari.sh> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-8-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: Add MSM8953 device treeVladimir Lypak1-0/+1326
Add a base DT for MSM8953 SoC. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Co-developed-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-7-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensorNikita Travkin1-0/+23
L8150 uses LTR559 as a light and proximity sensor. Add it to the devicetree. Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220219145140.84712-1-nikita@trvn.ru
2022-02-24arm64: dts: qcom: align Google CROS EC PWM node name with dtschemaKrzysztof Kozlowski5-5/+5
dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220214081916.162014-4-krzysztof.kozlowski@canonical.com
2022-02-24arm64: tegra: Enable Jetson Xavier NX USB device modeWayne Chang1-0/+25
This commit enables USB device mode at J5 micro-B USB port of Jetson Xavier NX. Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable UART instance on 40-pin headerkartik1-0/+6
On P3737 board, UART-A is available on 40-pin header. Enable UART-A for P3737 and change the compatible string to "nvidia,tegra194-hsuart". This allows supporting HW flow control and is the preferred choice for higher baud rates. Signed-off-by: kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add HDA device tree node for Tegra234Mohan Kumar2-0/+21
Add HDA device tree node for Tegra234 chip and for Jetson AGX Orin platform. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable device-tree overlay supportJon Hunter1-0/+11
Add the '-@' DTC option for the Jetson TX1, Jetson Nano, Jetson TX2, Jetson TX2 NX, Jetson AGX Xavier, Jetson Xavier NX and Jetson AGX Orin platforms. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays on these platforms. These Jetson platforms have various expansion headers, including a 40-pin GPIO header, that allow various add-on modules to be connected and this permits users to create device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB from between 30-50%. For example, with v5.17-rc1 increase in size is as follows: tegra210-p2371-2180.dtb: 79580 -> 105744 bytes tegra210-p3450-0000.dtb: 57465 -> 81357 bytes tegra186-p2771-0000.dtb: 64763 -> 99553 bytes tegra186-p3509-0000+p3636-0001.dtb: 48078 -> 62464 bytes tegra194-p2972-0000.dtb: 75303 -> 111545 bytes tegra194-p3509-0000+p3668-0000.dtb: 74762 -> 111995 bytes tegra194-p3509-0000+p3668-0001.dtb: 74578 -> 111748 bytes tegra234-p3737-0000+p3701-0000.dtb: 11229 -> 12917 bytes Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: APE sound card for Jetson AGX OrinSameer Pujar2-0/+1797
Add audio-graph based sound card support on Jetson AGX Orin platform. The sound card binds following modules: * I/O interfaces such as I2S and DMIC (to be specific I2S1, I2S2, I2S4, I2S6 and DMIC3 instances). * HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all the available instances). Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add audio devices on Tegra234Sameer Pujar1-0/+419
Add following devices which are part of APE subsystem * ACONNECT, AGIC and ADMA * AHUB and children (ADMAIF, I2S, DMIC, DSPK, MVC, SFC, AMX, ADX and Mixer) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Move audio IOMMU properties to ADMAIF nodeThierry Reding1-5/+4
The ADMAIF node represents the device that accesses memory in the Tegra audio subsystem, so that's where the iommus and interconnects properties should reside. Move them out of the sound card node and into the ADMAIF node to properly reflect the memory data path. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add Tegra234 IOMMUsThierry Reding1-0/+426
The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by isochronous memory clients and two dual-instance ARM SMMUs used by non- isochronous memory clients. Add the corresponding device tree nodes and hook up existing memory clients (SDHCI and BPMP). Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable gpio-keys on Jetson AGX Orin Developer KitThierry Reding2-0/+32
Expose power, force-recovery and sleep buttons via a gpio-keys device so that userspace can receive events from them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add GPCDMA node for tegra186 and tegra194Akhil R2-0/+85
Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target. Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add Tegra234 PWM devicetree nodesAkhil R1-0/+12
Add device tree nodes for Tegra234 PWM Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add Tegra234 I2C devicetree nodesAkhil R1-0/+121
Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: dts: renesas: Align GPIO hog names with dtschemaGeert Uytterhoeven7-9/+9
Dtschema expects GPIO hogs to end with a "hog" suffix. Also, the convention for node names is to use hyphens, not underscores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/baee4b9980576ffbab24122fce7147c9cbc2ea59.1645705998.git.geert+renesas@glider.be
2022-02-24arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdogBiju Das1-0/+14
Enable watchdog{0, 1, 2} interfaces on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220223165813.24833-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-23arm64: dts: qcom: Add support for Samsung Galaxy Book2Xilin Wu3-1/+750
Add support for Samsung Galaxy Book2 (W737) tablets. Currently working features: - Bootloader preconfigured display at 1280p - UFS - Wacom Digitizer - Two USB 3 ports - Sound - Bluetooth - Wi-Fi Signed-off-by: Xilin Wu <wuxilin123@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220223145130.544586-1-wuxilin123@gmail.com
2022-02-23arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1Dmitry Baryshkov1-5/+5
Convert all device tree xo_board users to the RPM_SMD_BB_CLK1 clock. Note, that xo_board can not be removed (yet), as clk-smd-rpm uses xo_board internally as the parent for all the clocks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-6-dmitry.baryshkov@linaro.org
2022-02-23arm64: dts: qcom: msm8996: add cxo and sleep-clk to gcc nodeDmitry Baryshkov1-2/+4
Supply proper cxo (RPM_SMD_BB_CLK1) and sleep_clk to the gcc clock controller node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-5-dmitry.baryshkov@linaro.org
2022-02-23arm64: dts: qcom: sdm845: add bi_tcxo to camccDmitry Baryshkov1-0/+2
Declare TCXO clock used for the Camera Clock Controller on SDM845. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-4-dmitry.baryshkov@linaro.org
2022-02-23arm64: dts: qcom: sdm845: enable dma for spiVinod Koul2-0/+15
Add dmas property for spi@880000 and pinconf setting so that we can use dma for this spi device. Also, add iommu properties for qup and spi. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222041951.1185186-2-vkoul@kernel.org
2022-02-23arm64: dts: qcom: sdm845: Add gsi dma nodeVinod Koul1-0/+46
This add the device node for gsi dma0 instances found in sdm845. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222041951.1185186-1-vkoul@kernel.org
2022-02-24arm64: dts: rockchip: align Google CROS EC PWM node name with dtschemaKrzysztof Kozlowski1-1/+1
dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20220214081916.162014-5-krzysztof.kozlowski@canonical.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10Michael Riesch1-1/+30
Enable the Rockchip RK809 audio codec on the Rockchip RK3568 EVB1-V10. This requires the VCCIO_ACODEC voltage regulator to be set to always on. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220222175004.1308990-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: set vdd_gpu regulator on rk3568-evb1-v10 to always onMichael Riesch1-0/+1
As discussed in [0], the Rockchip power domain driver does not consider the external supplies (such as VDD_GPU on the RK3568 EVB1). In the scope of this discussion it has been pointed out that turning this voltage on/off on the fly is not explicitly supported. This patch follows the other RK356x boards by example and sets the vdd_gpu regulator to always on. [0] https://lore.kernel.org/linux-rockchip/20211217130919.3035788-1-s.hauer@pengutronix.de/ Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220223112008.1316132-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: add the vdd_cpu regulator to rk3568-evb1-v10Michael Riesch1-0/+33
The TCS4525 voltage regulator provides the vdd_cpu on the Rockchip RK3568 EVB1. Add the device tree node and connect it to the CPU nodes. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220223162054.1626257-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24arm64: dts: rockchip: enable work led on rk3568-evb1-v10Michael Riesch1-0/+20
Enable the blue work LED on the Rockchip RK3568 EVB1-V10. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220222175004.1308990-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-23arm64: dts: qcom: sc7280: Add cpu OPP tablesSibi Sankar1-0/+230
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644428757-25575-1-git-send-email-quic_sibis@quicinc.com
2022-02-23arm64: dts: qcom: sc7280: Add EPSS L3 interconnect providerOdelu Kukatla1-0/+8
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Acked-by: Georgi Djakov <djakov@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1634812857-10676-4-git-send-email-okukatla@codeaurora.org
2022-02-23arm64: dts: exynos: Add initial device tree support for Exynos7885 SoCDavid Virag4-4/+1375
Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F". Currently this includes some clock support, UART support, and I2C nodes. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20220221194958.117361-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-02-22arm64: dts: ti: k3-*: Drop address and size cells from flash nodesPratyush Yadav6-12/+0
Specifying partitions directly under the flash nodes is deprecated. A partitions node should used instead. The address and size cells are not needed. Remove them. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Apurva Nandan<a-nandan@ti.com> Link: https://lore.kernel.org/r/20220217181025.1815118-2-p.yadav@ti.com
2022-02-22arm64: dts: ti: k3-*: Fix whitespace around flash@0 nodesPratyush Yadav5-5/+5
The OSPI flash nodes are missing a space before the opening brace. Fix that. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Apurva Nandan<a-nandan@ti.com> Link: https://lore.kernel.org/r/20220217181025.1815118-1-p.yadav@ti.com
2022-02-22arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regsNishanth Menon2-1/+5
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-6-nm@ti.com
2022-02-22arm64: dts: ti: k3-am64: Fix gic-v3 compatible regsNishanth Menon2-1/+5
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com
2022-02-22arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regsNishanth Menon2-1/+5
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-4-nm@ti.com
2022-02-22arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regsNishanth Menon2-1/+5
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org # 5.10+ Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com
2022-02-22arm64: dts: ti: k3-am65: Fix gic-v3 compatible regsNishanth Menon2-1/+5
Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org # 5.10+ Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-2-nm@ti.com
2022-02-22arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for wkup_gpioX instancesKeerthy1-2/+2
The interrupt-parent for wkup_gpioX instances are wrongly assigned as main_gpio_intr instead of wkup_gpio_intr. Fix it. Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20220203132647.11314-1-a-govindraju@ti.com
2022-02-22arm64: dts: renesas: spider-cpu: Enable watchdog timerGeert Uytterhoeven1-0/+5
Enable the watchdog timer on the Spider board. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/b36b2bb5770e10d906571721a3d73ca205b6f56e.1642525158.git.geert+renesas@glider.be
2022-02-22arm64: dts: renesas: r8a779f0: Add RWDT nodeGeert Uytterhoeven1-0/+10
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/556a7f41bdadceecbe8b59b79ac7e9f592ca17a2.1642525158.git.geert+renesas@glider.be
2022-02-21arm64: dts: juno: Add separate SCMI variantsRobin Murphy5-1/+255
While Juno's SCP firmware initially spoke the SCPI protocol, binary releases since 2018, and the newer open-source codebase, only speak SCMI and thus aren't particularly compatibile with the DTs we currently have upstream. Add a parallel set of variant DTs for boards with up-to-date firmware, replacing the SCPI parts with their new SCMI equivalents. Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-02-21arm64: dts: renesas: ulcb-kf: fix wrong commentNikita Yushchenko1-1/+1
Fix comment referencing salvator board, likely a copy-paste leftover. ulcb-kf.dtsi has nothing to do with salvator. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Fixes: 80c07701d5918928 ("arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec") Link: https://lore.kernel.org/r/20220216181003.114049-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21arm64: dts: meson: add support for OSMC Vero 4K+Christian Hewitt2-0/+118
The OSMC Vero 4K+ device is based on the Amlogic S905D (P230) reference design with the following specifications: - 2GB DDR4 RAM - 16GB eMMC - HDMI 2.1 video - S/PDIF optical output - AV output - 10/100/1000 Ethernet - AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2) - 2x USB 2.0 ports (1x OTG) - IR receiver (internal) - IR extender port (external) - 1x micro SD card slot - 1x Power LED (red) - 1x Reset button (in AV jack) Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Chad Wagner <wagnerch42@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-4-christianshewitt@gmail.com
2022-02-21arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMCJonas Kuenstler1-0/+2
Set the usdhc root clock to 400MHz to be able to support HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM. Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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