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2022-02-21arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4Teresa Remmet1-2/+2
LDO4 is not connected so disable it. And LDO5 is used for VSEL of the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an impact on the functionality. We enable it, as it is used. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltageTeresa Remmet1-0/+2
Add bindings for VDD_ARM (BUCK2) run and standby voltage. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Update WDOG muxingTeresa Remmet1-1/+1
To be able to trigger a reset also from an external source we need to configure the WDOG pin as open drain. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx linesTeresa Remmet1-6/+6
Reduce drive strength on fec tx lines for signal quality improvements. Measurements showed that TD0 and TD1 require X4 and the other lines X2 for optimized settings. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strengthTeresa Remmet1-8/+8
Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal improvement. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phyTeresa Remmet1-0/+1
To fit spec requirements set minimum output impedance for dp83867 ethernet phy. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 cameraTim Harvey2-0/+95
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 cameraTim Harvey2-0/+95
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio controlled regulator enable. Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modesTim Harvey4-0/+181
The imx8mm-venice-gw72xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw72xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modesTim Harvey4-0/+183
The imx8mm-venice-gw73xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw73xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts supportTim Harvey2-0/+837
The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: ls1028a: add efuse nodeMichael Walle1-0/+11
Layerscape SoCs contain a Security Fuse Processor which is basically a efuse controller. Add the node, so userspace can read the efuses. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-evk: add support for I2C5Hugo Villeneuve1-0/+22
Add support for i2c5, which is used to access the external I2C bus on connector J22 of the imx8mp-evk. Limit the speed to 100kHz since this is an external I2C bus. Disabled by default, since it is shared with the CAN1 bus. To enable i2c5, you need to disable the CAN1 function, enable the i2c5 function and also configure the CAN1/I2C5_SEL GPIO to HIGH to select i2c5 instead of CAN1. This can be done by defining a gpio-hog inside the pca6416 node, in your board device tree, like in this example: &flexcan1 { status = "disabled"; }; &i2c5 { status = "okay"; }; &pca6416 { can1-i2c5-sel-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; line-name = "can1-i2c5-sel"; }; }; Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-evk: add PCA6416 gpio line namesHugo Villeneuve1-0/+16
Add gpio-line-names for the various GPIO's connected to the PCA6416 I/O expander on the imx8mp EVK. This helps when using the new gpiod interface to find the GPIOs by name. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8qm: added more serial alias to dtsOliver Graute1-0/+3
Add more serial alias to imx8qm.dtsi file Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8qm: add compatible string for usdhc3Oliver Graute1-0/+4
add compatible string for usdhc3 Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Fabio Estevam <festevam@gmail.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-19arm64: dts: rockchip: fix supplies for pwm regulatorsHeiko Stuebner8-8/+8
The supply-name for pwm-regualators is "pwm", so the property needs to be pwm-supply, not vin-supply as in a number of boards. In all cases changed here, the supplying regulator is always an always-on fixed-regulator, so there will be no functional change and only a change in the regulator hirarchy, as can be seen for example in the regulator-summary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211227234529.1970281-2-heiko@sntech.de
2022-02-19arm64: dts: rockchip: define vdd_log on rk3399-pumaHeiko Stuebner1-0/+11
vdd_log supplied a lot of the logic parts of the soc and is supplied through pwm2. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211227234529.1970281-1-heiko@sntech.de
2022-02-18Merge tag 'juno-fix-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixesArnd Bergmann1-2/+1
Arm Juno fix for v5.17 Just a single fix to address coherency issue reported[1] by removing the GICv2m address from the DMA ranges as it loose coherency if mapped as cacheable at the SMMU due to the attribute combining rules. The GICv2m range is normally programmed for Device memory attributes. [1] https://lore.kernel.org/stable/0a1d437d-9ea0-de83-3c19-e07f560ad37c@arm.com/ * tag 'juno-fix-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Remove GICv2m dma-range Link: https://lore.kernel.org/r/20220214142615.2375269-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-18Merge tag 'socfpga_dts_update_for_v5.18_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixesArnd Bergmann1-2/+2
SoCFPGA dts updates for v5.18, part 2 - Add the "intel,socfpga-agilex-hsotg" compatible for Agilex platform * tag 'socfpga_dts_update_for_v5.18_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg" dt-bindings: usb: dwc2: add compatible "intel,socfpga-agilex-hsotg" Link: https://lore.kernel.org/r/20220211112556.98940-2-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-17Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski13-52/+40
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-02-16arm64: dts: ti: k3-am64: Add ESM0 to device memory mapHari Nagalla1-0/+1
AM64x SoCs have two ESM modules, with one in MAIN voltage domain and the other in MCU voltage domain. The error output from Main ESM module can be routed to the MCU ESM module. The error output of MCU ESM can be configured to reset the device. The MCU ESM configuration address space is already opened and this patch opens the MAIN ESM configuration address space. For ESM details please refer technical reference manual at https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Link: https://lore.kernel.org/r/20220210172246.27871-1-hnagalla@ti.com
2022-02-16arm64: dts: ti: k3-am65*: Remove #address-cells/#size-cells from flash nodesMatthias Schiffer2-8/+2
Specifying partitions directly in the flash node is deprecated, a fixed-partitions node should be used instead. Therefore, it doesn't make sense to have these properties in the flash nodes. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20220203140240.973690-2-matthias.schiffer@ew.tq-group.com
2022-02-15arm64: dts: broadcom: bcm4908: add I2C blockRafał Miłecki1-0/+9
BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-02-14arm64: dts: qcom: c630: disable crypto due to serrorSteev Klimaszewski1-0/+5
Disable the crypto block due to it causing an SError in qce_start() on the C630, which happens upon every boot when cryptomanager tests are enabled. Signed-off-by: Steev Klimaszewski <steev@kali.org> [bjorn: Reworked commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211105035235.2392-1-steev@kali.org
2022-02-14Merge 5.17-rc4 into usb-nextGreg Kroah-Hartman13-52/+40
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-14arm64: dts: imx8ulp: Set #thermal-sensor-cells to 1 as requiredSudeep Holla1-1/+1
The SCMI binding clearly states the value of #thermal-sensor-cells must be 1. However arch/arm64/boot/dts/freescale/imx8ulp.dtsi sets it 0 which results in the following warning with dtbs_check: | arch/arm64/boot/dts/freescale/imx8ulp-evk.dt.yaml: scmi: | protocol@15:#thermal-sensor-cells:0:0: 1 was expected | From schema: Documentation/devicetree/bindings/firmware/arm,scmi.yaml Fix it by setting it to 1 as required. Cc:Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Fixes: a38771d7a49b ("arm64: dts: imx8ulp: add scmi firmware node") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-14arm64: dts: imx8mm: Fix VPU HangingAdam Ford1-1/+0
The vpumix power domain has a reset assigned to it, however when used, it causes a system hang. Testing has shown that it does not appear to be needed anywhere. Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-13arm64: dts: imx8mq-evk: Add second PCIe port supportRichard Zhu1-0/+38
Enable the second PCIe port support on i.MX8MQ EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-12arm64: dts: exynos: use dedicated wake-up pinctrl compatible in Exynos850Krzysztof Kozlowski1-2/+2
Older Samsung Exynos SoC pin controller nodes (Exynos3250, Exynos4, Exynos5, Exynos5433) with external wake-up interrupts, expected to have one interrupt for multiplexing these wake-up interrupts. Also they expected to have exactly one pin controller capable of external wake-up interrupts. It seems however that newer ARMv8 Exynos SoC like Exynos850 and ExynosAutov9 have differences: 1. No multiplexed external wake-up interrupt, only direct, 2. More than one pin controller capable of external wake-up interrupts. Use dedicated Exynos850 compatible for its external wake-up interrupts controller to indicate the differences. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20220111201722.327219-21-krzysztof.kozlowski@canonical.com
2022-02-12arm64: dts: exynos: align pinctrl with dtschema in Exynos850Krzysztof Kozlowski1-28/+28
Align the pin controller related nodes with dtschema. No functional change expected. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20220111201722.327219-13-krzysztof.kozlowski@canonical.com
2022-02-12arm64: dts: exynos: drop incorrectly placed wakeup interrupts in Exynos850Krzysztof Kozlowski1-40/+0
The pin controller device node is expected to have one (optional) interrupt. Its pin banks capable of external interrupts, should define interrupts for each pin, unless a muxed interrupt is used. Exynos850 defined the second part - interrupt for each pin in wake-up pin controller - but also added these interrupts in main device node, which is not correct. Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211230195325.328220-3-krzysztof.kozlowski@canonical.com
2022-02-12arm64: dts: imx8mm-beacon: Enable PCIeAdam Ford1-0/+57
The baseboard supports a PCIe slot with a 100MHz reference clock, but it's controlled by a different GPIO, so a gated clock is required. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-12arm64: dts: rockchip: Add Pine64 PineNote boardSamuel Holland4-0/+677
The PineNote is a tablet from Pine64 based on the RK3566 SoC, featuring 4G/128G of storage, a 10.3" electrophoretic display (EPD) with two-color frontlight, both EMR and capacitive digitizers, dual-band wireless, quad-channel digital microphones, and stereo speakers. There are two existing variants of the board. v1.1 was contained in some early samples, and v1.2 was sold as the "PineNote Developer Edition". Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220130053803.43660-3-samuel@sholland.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-12arm64: dts: rockchip: Add pdm node to rk356xSamuel Holland1-0/+21
rk356x contains a PDM microphone controller which is compatible with the existing rockchip,pdm binding. Add its node. Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220130053803.43660-2-samuel@sholland.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-11arm64: dts: broadcom: bcm4908: add watchdog blockRafał Miłecki1-0/+9
BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt" binding which matches the first SoC with that block. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-02-11arm64: dts: broadcom: Add reference to RPi Zero 2 WStefan Wahren2-1/+4
This adds a reference to the dts of the Raspberry Pi Zero 2 W, so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-02-11arm64: dts: rockchip: enable the tsadc on rk3568-evb1-v10Michael Riesch1-0/+6
Enable the thermal adc on the Rockchip RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220209215549.94524-6-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-11arm64: dts: rockchip: enable the gpu on rk3568-evb1-v10Michael Riesch1-0/+5
Enable the GPU core on the Rockchip RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> [moved tsadc into a separate patch] Link: https://lore.kernel.org/r/20220209215549.94524-6-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-11arm64: dts: rockchip: enable the gpu on quartz64-aEzequiel Garcia1-0/+5
Enable the GPU core on the Pine64 Quartz64 Model A. Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220209215549.94524-5-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-11arm64: dts: rockchip: add cooling map and trip points for gpu to rk356xAlex Bee1-0/+26
RK356x SoCs have a second thermal sensor for the GPU. This adds the cooling map and trip points for it to make use of its contribution as a cooling device. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220209215549.94524-4-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-11arm64: dts: rockchip: add gpu node to rk356xEzequiel Garcia1-0/+49
Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core which is based on the Bifrost architecture. It has one shader core and two execution engines. Quoting the datasheet: Mali-G52 1-Core-2EE * Support 1600Mpix/s fill rate when 800MHz clock frequency * Support 38.4GLOPs when 800MHz clock frequency Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220209215549.94524-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-11arm64: dts: freescale: add initial support for verdin imx8m miniMarcel Ziswiler10-0/+1726
This patch adds the device tree to support Toradex Verdin iMX8M Mini a computer on module which can be used on different carrier boards. The module consists of an NXP i.MX 8M Mini family SoC (either i.MX 8M Mini Quad or 8M Mini DualLite), a PCA9450A PMIC, a Gigabit Ethernet PHY, 1 or 2 GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, an optional SPI CAN controller plus an optional Bluetooth/ Wi-Fi module. Anything that is not self-contained on the module is disabled by default. The device tree for the Dahlia includes the module's device tree and enables the supported peripherals of the carrier board. The device tree for the Verdin Development Board includes the module's device tree as well as the Dahlia one as it is a superset and supports almost all peripherals available. So far there is no display functionality supported at all but basic console UART, PCIe, USB host, eMMC and Ethernet and PCIe functionality work fine. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-11arm64: dts: imx8mp-evk: add PCA6416 interrupt controller modeHugo Villeneuve1-0/+12
Add interrupt controller mode for the pca6416 on i.MX8MP EVK board's. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-11arm64: dts: freescale: Use overlay target for simplicityShawn Guo1-15/+14
With commit 15d16d6dadf6 ("kbuild: Add generic rule to apply fdtoverlay"), overlay target can be used to simplify the build of DTB overlays. It also performs a cross check to ensure base DT and overlay actually match. Signed-off-by: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
2022-02-11arm64: dts: fsl-ls1028a-qds: Drop overlay syntax hard codingShawn Guo6-400/+296
As suggested by commit 9ae8578b517a ("of: Documentation: change overlay example to use current syntax"), there is no need to have overlay syntax be hard coded in the device tree source file any more. Signed-off-by: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
2022-02-11arm64: dts: imx8mm: fix strange hex notationMarcel Ziswiler1-3/+3
Fix strange hex notation with mixed lower-case and upper-case letters. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-11arm64: dts: qcom: sc7280: Set the default dr_mode for usb2Souradeep Chowdhury1-0/+4
Set the default dr_mode for usb2 node to "otg" to enable role-switch for EUD(Embedded USB Debugger) connector node. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Link: https://lore.kernel.org/r/22fb3bbc16f3a0ae894068e4420e08ea86389817.1644339918.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-11arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connectorSouradeep Chowdhury1-0/+36
Add the Embedded USB Debugger(EUD) device tree node. The node contains EUD base register region and EUD mode manager register regions along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. Also add the role-switch property to dwc3 node. Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Link: https://lore.kernel.org/r/b2b6bdf0e7589a7b6a6f9b390b227339636e0da9.1644339918.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-11arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"Dinh Nguyen1-2/+2
The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg" compatible. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20220125161821.1951906-3-dinguyen@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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