| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
According to the datasheet the VSC8531 PHY expects a reset pulse of 100 ns
and a delay of 15 ms after the reset has been deasserted. Set the matching
values in the devicetree.
Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains are fully functional.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add the DT node for the VPU blk-ctrl. With this in place the
VPU power domains are fully functional.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:
etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.
[lst]: Added power domains and switched clock assignments to the
new clock defines used for the composite clocks, instead of
relying on the backwards compat defines.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Now that we have support for the power domain controller on the i.MX8MM
we can put the USB controllers in their respective power domains to allow
them to power down the PHY when possible.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Fix invalid M2_RST# gpio pinmux.
Fixes: ef484dfcf6f7 ("arm64: dts: imx: Add i.mx8mm/imx8mn Gateworks gw7902 dts support")
Cc: stable@vger.kernel.org
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
The internal Ethernet switch suffers from erratum A-050484 ("Ethernet
flow control not functional on L2 switch NPI port when XFH is used").
XFH stands for "Extraction Frame Header" - which basically means the
default "ocelot" DSA tagging protocol.
However, the switch supports one other tagging protocol - "ocelot-8021q",
and this is not subject to the erratum above. So describe the hardware
ability to pass PAUSE frames in the device tree, and let the driver
figure out whether it should use flow control on the CPU port or not,
depending on whether the "ocelot" or "ocelot-8021q" tagging protocol is
being used.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
The 'interrupt-map' in several Layerscape SoCs is malformed. The
'#address-cells' size of the parent interrupt controller (the GIC) is not
accounted for.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Li Yang <leoyang.li@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add new properties to USB PHYs needed for enabling USB OTG mode.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
In linux both are identical, phy-mode is used more often, though. Also
for the ls1028a both phy-connection-type and phy-mode was used, one for
the enetc nodes and the other for the switch nodes. Unify them. But the
main reason for this is that the device tree files can be shared with
the u-boot ones; there the enetc driver only supports the "phy-mode"
property.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Move the PHY nodes from the network controller to the dedicated MDIO
controller. According to Vladimir Oltean direct MDIO access via the PF,
that is when the PHY is put under the "mdio" subnode, is defeatured and
in fact the latest reference manual isn't mentioning it anymore.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
One of the last devices which are enabled by default are the USB
controllers. Although the pins are not multi-function pins, some boards
might not use USB at all. Apply the "disabled-by-default" style also for
the USB controllers and enable the controllers in the actual device tree
of the boards.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Recently, support for this particular Vivante GC7000 GPU was added to the
linux kernel. Add the corresponding device tree node.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
On the LS1028A this instance of the eSDHC controller is intended for
either an eMMC or eSDIO card. It doesn't provide a card detect pin and
its IO voltage is fixed at 1.8V.
Remove the bogus broken-cd property, instead add the non-removable
property. Fix the voltage-ranges property and set it to 1.8V only.
Fixes: 491d3a3fc113 ("arm64: dts: ls1028a: Add esdhc node in dts")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
The buck2 output of the PMIC is the VDD core voltage of the cpu.
Switching off this will poweroff the CPU. Add the 'regulator-always-on'
property to avoid this.
Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add memory nodes for S32G-VNP-EVB and S32G-VNP-RDB2.
Signed-off-by: Chester Lin <clin@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add initial device-trees of NXP S32G2's Evaluation Board (S32G-VNP-EVB)
and Reference Design 2 Board (S32G-VNP-RDB2).
Signed-off-by: Chester Lin <clin@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Add an initial dtsi file for generic SoC features of NXP S32G2.
Signed-off-by: Chester Lin <clin@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
The NXP BlueBox3 is a prototyping board for high-performance autonomous
driving systems. It contains two Linux systems, running on the
LX2160A and the other on the S32G2 SoC. This patch adds the device tree
support for the LX2160A SoC.
In terms of networking from the LX2160A's perspective, there are:
- 4 RJ45 10G ports using Aquantia copper PHYs which are attached
directly to DPAA2 ports on the LX2160A
- 3 NXP SJA1110 automotive Ethernet switches. First two are managed by
the LX2160A (each switch has a host port towards a dpmac), the third
switch is managed by the S32G2. All 3 switches are interconnected
through on-board SERDES lanes. The cascade ports between the 2
switches managed by LX2160A form a DSA link, the cascade ports between
the LX2160A and the S32G2 domain form user ports (the "to_sw3" net
device).
- 2 RJ45 1G ports using Atheros copper PHYs which are attached directly
to NXP SJA1110 switches
- 12 automotive 100base-T1 single-pair Ethernet ports routed from the
SJA1110 internal PHY ports (TJA1103)
- One SGMII SERDES lane towards an internal connector, attached to one
of the SJA1110 switch ports
On board rev A, the AR8035 RGMII PHY addresses were different than on
rev B and later. This patch introduces a separate device tree for rev A.
The main device tree is supposed to cover rev B and later.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Co-developed-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Co-developed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Co-developed-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Co-developed-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Co-developed-by: Heinz Wrobel <Heinz.Wrobel@nxp.com>
Signed-off-by: Heinz Wrobel <Heinz.Wrobel@nxp.com>
Co-developed-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Co-developed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"),
for all PP command, it only support 1-1-1 mode, no matter the tx setting
in dts. But after the upper commit, the logic change. It will choose
the best mode(fastest mode) which flash device and spi-nor host controller
both support.
qspi and fspi host controller do not support read 1-4-4 mode. so need to
set the tx to 1, let the common code finally select read 1-1-4 mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
There are couple of revisions of SOMs (k26) and associated carrier cards
(kv260).
SOM itself has two major versions:
sm-k26 - SOM with EMMC
smk-k26 - SOM without EMMC used on starter kit with preprogrammed firmware
in QSPI.
SOMs are describing only devices available on the SOM or connections which
are described in specification (for example UART, fwuen).
When SOM boots out of QSPI it uses limited number of peripherals defined by
the specification and present in sm(k)-k26 dtses.
Then a carrier card (CC) detection is happening and DT overlay is applied
to brings new functionality. That's why DT overlays are used. The name is
composed together with SOM name and CC name that's why DT overlays with
these names are generated to make sure they can be used together.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1ba32590670434b650bacf6410a65579dd30b38b.1632294439.git.michal.simek@xilinx.com
|
|
29.5V (29p5) is obviously wrong for regulator l4 and l5. Correct them
to be 2.95V (2p95). No functional change.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210926072215.27517-1-shawn.guo@linaro.org
|
|
Some multiline properties (spread out over multiple lines to keep length
in check) were not indented properly, leading to misalignment with the
items above. The DT file is still small enough to address this early in
the process.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210925141841.407257-1-marijn.suijten@somainline.org
|
|
At the moment, longcheer-l8150 is using a dummy extcon-usb-gpio device
that permanently enables USB gadget mode. This workaround allows USB
to work but is actually wrong and confusing. The "vbus-gpio" used there
refers to an unused (floating) GPIO that is pulled up to make
extcon-usb-gpio report USB gadget mode permanently.
Replace this with the new &pm8916_usbin extcon device that actually
reports if an USB cable is attached or not. This allows the USB PHY
to be turned off when there is no USB cable attached and is much
cleaner overall.
Fixes: 16e8e8072108 ("arm64: dts: qcom: Add device tree for Longcheer L8150")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210928112945.25310-3-stephan@gerhold.net
|
|
At the moment, USB gadget mode on MSM8916 works only with an extcon
device that reports the correct USB mode. This might be because the
USB PHY needs to be configured appropriately.
Unfortunately there is currently no simple approach to get such an
extcon device during early bring-up. The extcon device for USB VBUS
(i.e. gadget/peripheral mode) is typically provided by the charging
driver which is almost always very complex to port.
On pretty much all devices with PM8916, the USB VBUS is also connected
to the PM8916 "USB_IN" pad, no matter if they use the linear charger
integrated into PM8916 or not. The state of this pad can be checked
with the "USBIN_VALID" interrupt of PM8916.
The "qcom,pm8941-misc" binding exists to expose an "usb_vbus" and/or
"usb_id" interrupt from the PMIC as an extcon device.
Add a &pm8916_usbin node to pm8916.dtsi which can be used as simple
extcon device for devices that are currently lacking a proper charger
driver.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210928112945.25310-2-stephan@gerhold.net
|
|
While removing the size from the "reg" properties in pm8916.dtsi,
commit bd6429e81010 ("ARM64: dts: qcom: Remove size elements from
pmic reg properties") mistakenly also removed the second register
address for the rtc@6000 device. That one did not represent the size
of the register region but actually the address of the second "alarm"
register region of the rtc@6000 device.
Now there are "reg-names" for two "reg" elements, but there is actually
only one "reg" listed.
Since the DT schema for "qcom,pm8941-rtc" only expects one "reg"
element anyway, just drop the "reg-names" entirely to fix this.
Fixes: bd6429e81010 ("ARM64: dts: qcom: Remove size elements from pmic reg properties")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210928112945.25310-1-stephan@gerhold.net
|
|
Describe all Ethernet PHY reset GPIOs on R-Car Gen3 boards, to avoid
relying solely on boot loaders to bring PHYs out of reset.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3e6fd765850e8ef0980d8e98bc5f2126538d626f.1631177442.git.geert+renesas@glider.be
|
|
Add compatible values to Ethernet PHY subnodes representing Realtek
RTL8211E PHYs on RZ/G2 boards. This allows software to identify the PHY
model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/3b366e3dddd4d3cd7e89b92d3a8f78f6dc18e244.1631174218.git.geert+renesas@glider.be
|
|
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on R-Car Gen3 boards. This allows software to identify the
PHY model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/07bd7e04dda9e84cde0664980f0b1a6d69e03109.1631174218.git.geert+renesas@glider.be
|
|
Add compatible values to Ethernet PHY subnodes representing Atheros
AR8031 PHYs on RZ/G2 boards. This allows software to identify the PHY
model at any time, regardless of the state of the PHY reset line.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/3f1b58756f149f0c634c66abaecc88e699f4c3cc.1631174218.git.geert+renesas@glider.be
|
|
While networking works fine in RGMII mode when using the Linux generic
PHY driver, it fails when using the Atheros PHY driver.
Fix this by correcting the Ethernet PHY mode to RGMII-RXID, which works
fine with both drivers.
Fixes: a5200e63af57d05e ("arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling")
Reported-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2a4c15b2df23bb63f15abf9dfb88860477f4f523.1632465965.git.geert+renesas@glider.be
|
|
Update MSS node to support MSA based modem boot on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631886935-14691-11-git-send-email-sibis@codeaurora.org
|
|
This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631886935-14691-10-git-send-email-sibis@codeaurora.org
|
|
Add miscellaneous nodes to boot the modem and support post-mortem debug
on SC7280 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631886935-14691-9-git-send-email-sibis@codeaurora.org
|
|
Add, delete and update platform specific reserved memory nodes.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631886935-14691-8-git-send-email-sibis@codeaurora.org
|
|
Add missing reserved regions as described in v1 of SC7280 memory map.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631886935-14691-7-git-send-email-sibis@codeaurora.org
|
|
This device has a physical matrix keyboard, connected to a GPIO
expander, for which there's still no support yet.
Though, some of the keys are connected to the MSM8998 GPIOs and not
as a matrix, so these can be added.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123823.368199-4-angelogioacchino.delregno@somainline.org
|
|
This smartphone has a Goodix GT8296 touch IC, reachable at address
0x14 on blsp2 i2c-1.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123823.368199-3-angelogioacchino.delregno@somainline.org
|
|
Add configuration for the physical keyboard LEDs, including the
caps lock indicator and keyboard backlight.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123823.368199-2-angelogioacchino.delregno@somainline.org
|
|
Add device tree support for the F(x)tec Pro 1 (QX1000) smartphone;
this is a minimal configuration to boot to serial console.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210909123823.368199-1-angelogioacchino.delregno@somainline.org
|
|
At the moment, playing audio on Secondary MI2S will just end up getting
stuck, without actually playing any audio. This happens because the wrong
bit clock is configured when playing audio on Secondary MI2S.
The PRI_I2S_CLK (better name: SPKR_I2S_CLK) is used by the SPKR audio mux
block that provides both Primary and Secondary MI2S.
The SEC_I2S_CLK (better name: MIC_I2S_CLK) is used by the MIC audio mux
block that provides Tertiary MI2S. Quaternary MI2S is also part of the
MIC audio mux but has its own clock (AUX_I2S_CLK).
This means that (quite confusingly) the SEC_I2S_CLK is not actually
used for Secondary MI2S as the name would suggest. Secondary MI2S
needs to have the same clock as Primary MI2S configured.
Fix the clock list for the lpass node in the device tree and add
a comment to clarify this confusing naming. With these changes,
audio can be played correctly on Secondary MI2S.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 3761a3618f55 ("arm64: dts: qcom: add lpass node")
Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210816181810.2242-1-stephan@gerhold.net
|
|
So far there were no interrupts set up for the BMC150 accelerometer
+ magnetometer combo because they were broken for some reason.
It turns out Longcheer L8150 actually has a BMC156 which is very similar
to BMC150, but only has an INT2 pin for the accelerometer part.
This requires some minor changes in the bmc150-accel driver which is now
supported by using the more correct bosch,bmc156_accel compatible.
Unfortunately it looks like even INT2 is not functional on most boards
because the interrupt line is not actually connected to the BMC156.
However, there are two pads next to the chip that can be shorted
to make it work if needed.
While at it, add the missing interrupts for the magnetometer part
and extra BMG160 gyroscope, those seem to work without any problems.
Also correct the magnetometer compatible to bosch,bmc156_magn for clarity
(no functional difference for the magnetometer part).
Tested-by: Nikita Travkin <nikita@trvn.ru>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210816123544.14027-1-stephan@gerhold.net
|
|
Add IMEM and pil info DT nodes for SC7180 SoC which will help in the
post-mortem debug.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
[bjorn: Dropped dload-mode subnode, as no agreement was reached on this binding]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/39064a2db95ccc2cb5eef003569bef2de651c8ed.1628757036.git.saiprakash.ranjan@codeaurora.org
|
|
Add missing include to make it compile.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-17-konrad.dybcio@somainline.org
|
|
Add initial SM6350 SoC and Sony Xperia 10 III (PDX213, Lena platform) device
trees. There is no sign of another Lena devices on the horizon, so a common
DTSI is not created for now. 10 III features a Full HD OLED display and 5G
support, among other nice things like USB3.
The bootloader is VERY unpleasant, to get a bootable setup you have to run:
mkbootimg --kernel arch/arm64/boot/Image.gz --ramdisk [some initrd] \
--dtb arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dtb \
--cmdline "[some cmdline]" --base 0 --kernel_offset 0x8000 \
--ramdisk_offset 0x1000000 --dtb_offset 0x1f00000 --os_version 11 \
--os_patch_level "2021-08" --tags_offset 0x100 --pagesize 4096 \
--header_version 2 -o mainline.img
adb reboot bootloader
// You have to either pull vbmeta{"","_system"} from
// /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process
fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img
fastboot --disable-verity --disable-verification flash vbmeta_system \
vbmeta_system.img
fastboot flash boot mainline.img
fastboot erase dtbo // This will take approx 70s...
fastboot reboot
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-16-konrad.dybcio@somainline.org
|
|
Add a node for the APPS SMMU to allow for managing memory access to peripherals
such as the USB controller.
While at it, add iommus property to the USB1 node to make sure its registers can
be accessed, as they seem to be gated by default.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-15-konrad.dybcio@somainline.org
|
Frieder Schrempf
Lucas Stach
Tim Harvey
Vladimir Oltean
Rob Herring
Dmitry Osipenko
Michael Walle
Heiko Thiery
Chester Lin
Wasim Khan
Haibo Chen
Michal Simek
Shawn Guo
Marijn Suijten
Stephan Gerhold
Geert Uytterhoeven
Sibi Sankar
AngeloGioacchino Del Regno
Sai Prakash Ranjan
Konrad Dybcio