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2022-06-19arm64: dts: freescale: align gpio-key node names with dtschemaKrzysztof Kozlowski15-39/+39
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: imx8m: Disable job ring 0 nodesFabio Estevam4-0/+4
Now that the JR0 reservation is done in both upstream (v2.7) and downstream (NXP lf_v2.4) TF-A versions, the kernel fails to initialize the job ring 0: # dmesg | grep jr caam_jr 30901000.jr: failed to flush job ring 0 caam_jr: probe of 30901000.jr failed with error -5 Disable the sec_jr0 nodes by default to avoid the caam_jr probe error. Suggested-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: freescale: imx8qxp: Fix thermal zone name for cpu0Abel Vesa1-1/+1
The proper name is cpu0-thermal, not cpu-thermal0, so change it to that. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: mba8mx: Remove unneeded commentsFabio Estevam1-2/+0
The bootargs line is already commented out and the comment of UART4 does not apply, as uart4 node is not described. Remove both comments to make the dtsi cleaner. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-17arm64: dts: ti: Align gpio-key node names with dtschemaKrzysztof Kozlowski2-4/+4
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220616005333.18491-29-krzysztof.kozlowski@linaro.org
2022-06-17arm64: dts: ti: Adjust whitespace around '='Krzysztof Kozlowski13-28/+28
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org
2022-06-17arm64: dts: ti: k3-am64-main: Remove support for HS400 speed modeAswath Govindraju1-2/+0
AM64 SoC, does not support HS400 and HS200 is the maximum supported speed mode[1]. Therefore, fix the device tree node to reflect the same. [1] - https://www.ti.com/lit/ds/symlink/am6442.pdf (SPRSP56C – JANUARY 2021 – REVISED FEBRUARY 2022) Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220512064859.32059-1-a-govindraju@ti.com
2022-06-17arm64: dts: ti: k3-j721s2: Fix overlapping GICD memory regionMatt Ranostay1-1/+1
GICD region was overlapping with GICR causing the latter to not map successfully, and in turn the gic-v3 driver would fail to initialize. This issue was hidden till commit 2b2cd74a06c3 ("irqchip/gic-v3: Claim iomem resources") replaced of_iomap() calls with of_io_request_and_map() that internally called request_mem_region(). Respective console output before this patchset: [ 0.000000] GICv3: /bus@100000/interrupt-controller@1800000: couldn't map region 0 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: linux-stable@vger.kernel.org Cc: Marc Zyngier <maz@kernel.org> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220617151304.446607-1-mranostay@ti.com
2022-06-17arm64: dts: rockchip: rock-pi-s add more peripheralsSjoerd Simons1-0/+52
This enables the following peripherals: * Onboard ethernet support * Bluetooth * USB 2 port * OTG port via type-c connector * Hardware watchog Also add aliases for the mmc devices and the ethernet interface Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Link: https://lore.kernel.org/r/20220614064858.1445817-4-sjoerd@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-06-17arm64: dts: rockchip: add ROCK Pi S DTS supportAkash Gajjar2-0/+202
ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a, - 256MB/512MB DDR3 RAM - SD, NAND flash (optional on board 1/2/4/8Gb) - 100MB ethernet, PoE (optional) - Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module - USB2.0 Type-A HOST x1 - USB3.0 Type-C OTG x1 - 26-pin expansion header - USB Type-C DC 5V Power Supply This patch enables - Console - NAND Flash - SD Card Signed-off-by: Akash Gajjar <akash@openedev.com> [sjoerd: Sort dt nodes, drop properties duplicated from dtsi] Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Link: https://lore.kernel.org/r/20220614064858.1445817-3-sjoerd@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-06-17arm64: dts: mt8183: add GCE client property for Mediatek MUTEXMoudy Ho1-0/+1
In order to allow modules with latency requirements such as MDP3 to set registers through CMDQ, add the relevant dts property. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://lore.kernel.org/r/20220610063424.7800-6-moudy.ho@mediatek.com [mb: fix commit subject] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: mediatek: mt7622-bananapi-bpi-r64: align led node names with dtschemaKrzysztof Kozlowski1-2/+5
The node names should be generic and DT schema expects certain pattern with 'led'. Use generic color properties instead of the node name. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-16-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: mediatek: align gpio-key node names with dtschemaKrzysztof Kozlowski8-18/+18
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-15-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: mediatek: adjust whitespace around '='Krzysztof Kozlowski10-40/+40
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204402.832393-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: mediatek: mt8195: enable usb remote wakeupChunfeng Yun1-0/+8
Enable USB remote wakeup of all four xHCI controller Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220617072344.21461-2-chunfeng.yun@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: mediatek: mt8195: add efuse node and cellsChunfeng Yun1-0/+55
Add efuse node and cells used by t-phy to fix the bit shift issue Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220617072344.21461-1-chunfeng.yun@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: mt8183: add svs device informationRoger Lu1-0/+16
Add compatible/reg/irq/clock/efuse setting in svs node. Signed-off-by: Roger Lu <roger.lu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20220516004311.18358-3-roger.lu@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17arm64: dts: renesas: Fix thermal-sensors on single-zone sensorsGeert Uytterhoeven2-2/+2
"make dtbs_check": arch/arm64/boot/dts/renesas/r8a774c0-cat874.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[74], [0]] is too long arch/arm64/boot/dts/renesas/r8a774c0-ek874.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[79], [0]] is too long arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[82], [0]] is too long arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[87], [0]] is too long arch/arm64/boot/dts/renesas/r8a77990-ebisu.dtb: thermal-zones: cpu-thermal:thermal-sensors: [[105], [0]] is too long From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml Indeed, the thermal sensors on R-Car E3 and RZ/G2E support only a single zone, hence #thermal-sensor-cells = <0>. Fix this by dropping the bogus zero cell from the thermal sensor specifiers. Fixes: 8fa7d18f9ee2dc20 ("arm64: dts: renesas: r8a77990: Create thermal zone to support IPA") Fixes: 8438bfda9d768157 ("arm64: dts: renesas: r8a774c0: Create thermal zone to support IPA") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/28b812fdd1fc3698311fac984ab8b91d3d655c1c.1655301684.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connectorWolfram Sang2-0/+14
The schematics label it as SCIF0 debug port. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220614193005.2652-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add SCIF nodesLinh Phung1-0/+51
Extracted from a bigger patch in the BSP, rebased, reg length corrected, and DMA properties added. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220614095242.8264-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add HSCIF nodesLinh Phung1-0/+68
Extracted from a bigger patch in the BSP, rebased and DMA properties added. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220614095109.8175-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3Wolfram Sang1-0/+3
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220613134914.18655-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: Add missing space after remote-endpointNiklas Söderlund2-4/+4
Add the missing space after remote-endpoint in r8a774c0.dtsi and r8a77990.dtsi before the typo spreads to other files. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20220608175728.1012550-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: rzg2ul-smarc-som: Enable ADC on SMARC platformBiju Das1-0/+12
Enable the ADC found on RZ/G2UL SMARC SoM. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220608173025.22792-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: rzg2ul-smarc: Enable RSPI1 on carrier boardBiju Das3-6/+13
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file and drops deleting pinctl* properties from board DTS file. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220608173025.22792-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add CPU core clocksGeert Uytterhoeven1-0/+8
Describe the clocks for the eight Cortex-A55 CPU cores. CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ. CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ. For now no operating points are defined. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/c502087f9affa86dd665def0d990d277a51cc75c.1654701480.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: r8a779f0: Add CPUIdle supportTho Vu1-0/+21
Support CPUIdle for ARM Cortex-A55 on R-Car S4-8. Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/5310792ce4c06515a5373ff44ceb9b925f007489.1654701480.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU coresGeert Uytterhoeven1-5/+133
Complete the description of the Cortex-A55 CPU cores and L3 cache controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters. Based on patches in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/d6af5975090d5830cb053b52400439bd1cbe8fc7.1654701480.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: r8a779f0: Add L3 cache controllerGeert Uytterhoeven1-0/+8
Describe the cache configuration for the first Cortex-A55 CPU core on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: r8a779a0: Add CPU0 core clockGeert Uytterhoeven1-0/+1
Describe the clock for the first Cortex-A76 CPU core. For now no operating points are defined. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3ace4eea4ff1cdc0f7b8ea7d0433c1063d795785.1654701400.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible valuesGeert Uytterhoeven1-10/+20
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4: - GPIO. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b477eea0fc33a055d1b1874847e26614f68f5da0.1654701299.git.geert+renesas@glider.be
2022-06-17arm64: dts: renesas: rzg2l-smarc: Use proper bool operatorWolfram Sang1-1/+1
When checking for defined macros, we want the boolean AND not the binary one. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220603232940.21736-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add UFS nodeYoshihiro Shimoda1-0/+19
Add UFS node for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220603110524.1997825-7-yoshihiro.shimoda.uh@renesas.com [geert: Move ufs30-clk to preserve sort order] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodesYoshihiro Shimoda1-0/+16
Add iommus properties to the DMAC nodes for r8a779f0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220530024626.1870277-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add IPMMU nodesYoshihiro Shimoda1-0/+46
Add IPMMU nodes for r8a779f0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220530024626.1870277-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: Adjust whitespace around '='Krzysztof Kozlowski5-11/+11
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204231.832090-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17arm64: dts: renesas: r8a779f0: Add thermal supportLinh Phung1-0/+56
Add support for 3 TSC nodes of thermal. The 4th node is for the control domain and not for Linux. Signed-off-by: Linh Phung <linh.phung.jy@renesas.com> [wsa: rebased, fixed resource size, removed unused 4th node breaking probe] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220525151355.24175-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-16arm64: dts: microchip: adjust whitespace around '='Krzysztof Kozlowski2-124/+124
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204110.831805-1-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: sprd: adjust whitespace around '='Krzysztof Kozlowski3-8/+8
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Orson Zhai <orsonzhai@gmail.com> Link: https://lore.kernel.org/r/20220526204152.831948-1-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: hisilicon: adjust whitespace around '='Krzysztof Kozlowski6-23/+23
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204453.832681-1-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: marvell: adjust whitespace around '='Krzysztof Kozlowski4-6/+6
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204525.832847-1-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: lg: adjust whitespace around '='Krzysztof Kozlowski2-38/+38
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204606.833054-5-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: apm: adjust whitespace around '='Krzysztof Kozlowski2-3/+3
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204606.833054-3-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: amd: adjust whitespace around '='Krzysztof Kozlowski2-4/+4
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204606.833054-2-krzysztof.kozlowski@linaro.org
2022-06-15arm64: dts: Add DTS files for bcmbca SoC BCM6813William Zhang3-1/+160
Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the SoC description DTS header and bcm96813.dts is a simple DTS file for Broadcom BCM96813 Reference board that only enable the UART port. Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-06-15arm64: dts: Add support for Stratix 10 Software Virtual PlatformTeh Wen Ping2-1/+119
Add Stratix 10 Software Virtual Platform device tree Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-06-14arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro boardFrank Wunderlich1-0/+48
Add Device Tree node for mt7531 switch connected to gmac0. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-14arm64: dts: allwinner: align gpio-key node names with dtschemaKrzysztof Kozlowski4-8/+8
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220609113911.380368-4-krzysztof.kozlowski@linaro.org
2022-06-14arm64: dts: altera: adjust whitespace around '='Krzysztof Kozlowski1-1/+1
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-06-14arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECCNiravkumar L Rabara1-7/+7
Use defined GIC interrupt type instead of hard-coded numbers for ECC (Error Correction Code) memory, which creates edac sysfs interface. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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