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path: root/arch/arm64/include/asm/pgtable-hwdef.h (unfollow)
AgeCommit message (Expand)AuthorFilesLines
2019-02-28arm64: Add workaround for Fujitsu A64FX erratum 010001Zhang Lei1-0/+1
2018-12-28kasan, arm64: enable top byte ignore for the kernelAndrey Konovalov1-0/+1
2018-12-18KVM: arm64: Add support for creating PUD hugepages at stage 2Punit Agrawal1-0/+2
2018-12-18KVM: arm64: Support PUD hugepage in stage2_is_exec()Punit Agrawal1-0/+2
2018-12-12arm64: mm: Introduce MAX_USER_VA_BITS definitionWill Deacon1-5/+1
2018-12-10arm64: Kconfig: Re-jig CONFIG options for 52-bit VAWill Deacon1-2/+2
2018-12-10arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGDSteve Capper1-0/+10
2018-12-10arm64: Add TCR_EPD{0,1} definitionsMarc Zyngier1-0/+4
2018-09-18arm64: mm: Support Common Not Private translationsVladimir Murzin1-0/+2
2018-03-06arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=yWill Deacon1-0/+1
2018-01-16arm64: Correct type for PUD macrosPunit Agrawal1-3/+3
2018-01-08arm64: KVM: PTE/PMD S2 XN bit definitionMarc Zyngier1-0/+2
2017-12-22arm64: handle 52-bit physical addresses in page table entriesKristina Martsenko1-2/+4
2017-12-22arm64: head.S: handle 52-bit PAs in PTEs in early page table setupKristina Martsenko1-0/+6
2017-12-22arm64: handle 52-bit addresses in TTBRKristina Martsenko1-0/+13
2017-12-22arm64: limit PA size to supported rangeKristina Martsenko1-0/+2
2017-12-22arm64: add kconfig symbol to configure physical address sizeKristina Martsenko1-1/+1
2017-12-11arm64: mm: Move ASID from TTBR0 to TTBR1Will Deacon1-0/+1
2016-09-09arm64: simplify sysreg manipulationMark Rutland1-0/+1
2016-06-29arm64: Add PTE_HYP_XN page table flagMarc Zyngier1-0/+1
2016-05-06arm64: Ensure pmd_present() returns false after pmd_mknotpresent()Catalin Marinas1-1/+0
2016-04-21arm64: Reuse TCR field definitions for EL1 and EL2Suzuki K Poulose1-17/+63
2015-12-21arm64: hugetlb: add support for PTE contiguous bitDavid Woods1-1/+17
2015-10-19arm64: Introduce helpers for page table levelsSuzuki K. Poulose1-3/+36
2015-10-08arm64: PTE/PMD contiguous bit definitionJeremy Linton1-0/+9
2015-07-27arm64: Add support for hardware updates of the access and dirty pte bitsCatalin Marinas1-0/+3
2015-04-14arm64: expose number of page table levels on Kconfig levelKirill A. Shutemov1-3/+3
2015-03-23arm64: mm: increase VA range of identity mapArd Biesheuvel1-1/+6
2015-01-16KVM: arm64: ARMv8 header changes for page loggingMario Smarduch1-0/+1
2014-07-23arm64: Remove asm/pgtable-*level-hwdef.h filesCatalin Marinas1-6/+36
2014-07-23arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELSCatalin Marinas1-2/+2
2014-07-23arm64: mm: Implement 4 levels of translation tablesJungseok Lee1-2/+4
2014-07-23arm64: Introduce VA_BITS and translation level optionsJungseok Lee1-1/+1
2014-05-09arm64: mm: Create gigabyte kernel logical mappings where possibleSteve Capper1-0/+2
2014-04-03arm64: Update the TCR_EL1 translation granule definitions for 16K pagesCatalin Marinas1-1/+5
2014-03-13arm64: Add boot time configuration of Intermediate Physical Address sizeRadha Mohan Chintakuntla1-3/+2
2013-12-06arm64: mm: Fix PMD_SECT_PROT_NONE definitionSteve Capper1-1/+1
2013-10-17KVM: ARM: Support hugetlbfs backed huge pagesChristoffer Dall1-0/+2
2013-09-03arm64: mm: permit use of tagged pointers at EL0Will Deacon1-0/+1
2013-06-14ARM64: mm: THP support.Steve Capper1-0/+4
2013-06-14ARM64: mm: HugeTLB support.Steve Capper1-0/+8
2013-06-07arm64: KVM: define HYP and Stage-2 translation page flagsMarc Zyngier1-0/+19
2012-11-16arm64: Distinguish between user and kernel XN bitsCatalin Marinas1-2/+4
2012-09-17arm64: MMU definitionsCatalin Marinas1-0/+94