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AgeCommit message (Expand)AuthorFilesLines
2019-02-06arm64: Make PMR part of task contextJulien Thierry1-0/+3
2018-12-13arm64: ptr auth: Move per-thread keys from thread_info to thread_structWill Deacon1-0/+3
2018-12-13arm64: add prctl control for resetting ptrauth keysKristina Martsenko1-0/+4
2018-12-13arm64: expose user PAC bit positions via ptraceMark Rutland1-2/+0
2018-12-12arm64: mm: Introduce MAX_USER_VA_BITS definitionWill Deacon1-5/+1
2018-12-10arm64: Kconfig: Re-jig CONFIG options for 52-bit VAWill Deacon1-2/+2
2018-12-10arm64: mm: Allow forcing all userspace addresses to 52-bitSteve Capper1-1/+8
2018-12-10arm64: mm: introduce 52-bit userspace supportSteve Capper1-4/+9
2018-12-10arm64: mm: Define arch_get_mmap_end, arch_get_mmap_baseSteve Capper1-0/+7
2018-12-10arm64: mm: Introduce DEFAULT_MAP_WINDOWSteve Capper1-2/+8
2018-11-08arm64: mm: define NET_IP_ALIGN to 0Ard Biesheuvel1-0/+8
2018-10-31treewide: remove current_text_addrNick Desaulniers1-7/+0
2018-09-14arm64: cpu: Move errata and feature enable callbacks closer to callersWill Deacon1-4/+0
2018-09-14arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3Will Deacon1-0/+7
2018-07-26arm64: Add support for STACKLEAK gcc pluginLaura Abbott1-0/+15
2018-07-05arm64: use PSR_AA32 definitionsMark Rutland1-3/+3
2018-06-01arm64: signal: Report signal frame size to userspace via auxvDave Martin1-0/+5
2018-05-25arm64/sve: Move sve_pffr() to fpsimd.h and make inlineDave Martin1-1/+11
2018-05-25arm64/sve: Move read_zcr_features() out of cpufeature.hDave Martin1-0/+1
2018-05-25arm64: fpsimd: Eliminate task->mm checksDave Martin1-1/+3
2018-03-28arm64: uaccess: Fix omissions from usercopy whitelistDave Martin1-13/+25
2018-03-28arm64: fpsimd: Split cpu field out from struct fpsimd_stateDave Martin1-2/+2
2018-03-26arm64: capabilities: Update prototype for enable call backDave Martin1-3/+4
2018-02-06arm64: Make USER_DS an inclusive limitRobin Murphy1-0/+3
2018-01-16arm64: kernel: Prepare for a DISR userJames Morse1-0/+1
2018-01-15arm64: Implement thread_struct whitelist for hardened usercopyKees Cook1-0/+10
2017-11-03arm64/sve: Add prctl controls for userspace vector length managementDave Martin1-0/+4
2017-11-03arm64/sve: Support vector length resetting for new processesDave Martin1-0/+1
2017-11-03arm64/sve: Core task context handlingDave Martin1-0/+2
2017-10-02arm64: move TASK_* definitions to <asm/processor.h>Yury Norov1-0/+21
2017-08-15arm64: kernel: remove {THREAD,IRQ_STACK}_START_SPArd Biesheuvel1-1/+1
2017-08-07arm64: Abstract syscallno manipulationDave Martin1-1/+1
2017-08-07arm64: syscallno is secretly an int, make it officialDave Martin1-1/+1
2017-06-22arm64: ptrace: Flush user-RW TLS reg to thread_struct before readingDave Martin1-0/+3
2017-03-22arm64: struct debug_info: Check CONFIG_HAVE_HW_BREAKPOINTChris Redmon1-0/+2
2017-01-10arm64: Remove useless UAO IPI and describe how this gets enabledJames Morse1-1/+0
2016-11-17locking/core: Provide common cpu_relax_yield() definitionChristian Borntraeger1-2/+0
2016-11-16locking/core, arch: Remove cpu_relax_lowlatency()Christian Borntraeger1-1/+0
2016-11-16locking/core: Introduce cpu_relax_yield()Christian Borntraeger1-0/+1
2016-10-20arm64: cpufeature: Schedule enable() calls instead of calling them via IPIJames Morse1-3/+3
2016-09-01arm64: remove duplicate macro __KERNEL__ checkzijun_hu1-2/+0
2016-07-01arm64: trap userspace "dc cvau" cache operation on errata-affected coreAndre Przywara1-0/+1
2016-02-18arm64: kernel: Add support for User Access OverrideJames Morse1-0/+1
2016-02-16arm64: prefetch: add missing #include for spin_lock_prefetchWill Deacon1-0/+1
2016-02-16arm64: prefetch: don't provide spin_lock_prefetch with LSEWill Deacon1-2/+5
2015-10-21arm64: Delay cpu feature capability checksSuzuki K. Poulose1-1/+1
2015-07-27arm64: kernel: Add support for Privileged Access NeverJames Morse1-0/+2
2015-06-01arm64: context-switch user tls register tpidr_el0 for compat tasksWill Deacon1-1/+18
2015-03-17arm64: Implement cpu_relax as yieldPeter Crosthwaite1-1/+5
2015-02-27arm64: Increase the swiotlb buffer size 64MBCatalin Marinas1-1/+2