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2020-01-06Merge tag 'renesas-arm64-dt-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dtOlof Johansson32-866/+1333
Renesas ARM64 DT updates for v5.6 - Remove now unused ARCH_R8A7796 config symbol, - Rename R-Car H3 and M3-W SoC, and ULCB board DTS files to increase naming consistency, - Miscellaneous fixes for issues detected by "make dtbs_check", - Enhance support for R-Car M3-W+, - Display support for the EK874 board, - Prepare for split of R-Car H3 ES1.x and ES2.0+ config symbols, - Minor fixes and improvements. * tag 'renesas-arm64-dt-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Prepare for split of ARCH_R8A7795 into ARCH_R8A7795[01] arm64: dts: renesas: Sort DTBs in Makefile arm64: dts: renesas: Drop redundant SoC prefixes from ULCB DTS file names arm64: dts: renesas: Rename r8a7795{-es1,}* to r8a7795[01]* arm64: dts: renesas: Add EK874 board with idk-2121wr display support arm64: dts: renesas: r8a77961: Add SDHI nodes arm64: dts: renesas: r8a77961: Add I2C nodes arm64: dts: renesas: r8a77961: Add SYS-DMAC nodes arm64: dts: renesas: r8a77961: Add RAVB node arm64: dts: renesas: r8a77961: Add GPIO nodes arm64: dts: renesas: r8a77961: Add RWDT node arm64: dts: renesas: r8a77990: ebisu: Remove clkout-lr-synchronous from sound arm64: dts: renesas: r8a77970: Group tuples in thermal reg property arm64: dts: renesas: Group tuples in pci ranges and dma-ranges properties arm64: dts: renesas: Group tuples in interrupt properties arm64: dts: renesas: Group tuples in regulator-gpio states properties arm64: dts: renesas: Rename r8a7796* to r8a77960* arm64: dts: renesas: Remove use of ARCH_R8A7796 Link: https://lore.kernel.org/r/20200106104857.8361-4-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06arm64: dts: Add Unisoc's SC9863A SoC supportChunyan Zhang4-1/+642
Add basic DT to support Unisoc's SC9863A, with this patch, the board sp9863a-1h10 can run into console. Link: https://lore.kernel.org/r/20191223092948.24824-4-zhang.lyra@gmail.com Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06arm64: dts: rockchip: Add PX30 LVDSMiquel Raynal1-0/+37
Describe LVDS IP. Add the CRTC and LVDS relevant endpoints so they can be linked together. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191224143900.23567-12-miquel.raynal@bootlin.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-06arm64: dts: rockchip: add dsi controller for px30Heiko Stuebner1-0/+48
This adds the dw-mipi-dsi controller and hooks it into the display-subsystem on px30. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20200106112005.795834-1-heiko@sntech.de
2020-01-06arm64: dts: rockchip: Fix IR on Beelink A1Robin Murphy1-1/+2
Apparently I wasn't paying enough attention... And nor is the lazy test of `cat /dev/lirc0` sufficiently blunder-proof. Oh well, with the correct polarity, let's also hook up a keymap now that one for the standard Beelink remote has handily appeared. Fixes: 79702ded8c2f ("arm64: dts: rockchip: Add Beelink A1") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/44269c08e2a5d75b03ded87d2eb11621762d8249.1577636223.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-06arm64: dts: rockchip: Add PX30 DSI DPHYMiquel Raynal1-0/+12
Add the PHY which outputs MIPI DSI and LVDS. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20191224143900.23567-11-miquel.raynal@bootlin.com [added dsi power-domain, following vendor-kernel] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-06arm64: dts: allwinner: a64: pinebook: Fix lid wakeupSamuel Holland1-0/+2
By default, gpio-keys configures the pin to trigger wakeup IRQs on either edge. The lid switch should only trigger wakeup when opening the lid, not when closing it. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-05arm64: dts: qcom: sdm845: add the ufs resetVinod Koul1-0/+2
Add the core UFS reset for sdm845 Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-05arm64: dts: qcom: sm8150: Fix UFS phy register sizeVinod Koul1-1/+1
UFS phy register space size is 0x1c0. so update it Reported-by: Can Guo <cang@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-05arm64: dts: qcom: sm8150-mtp: Add UFS gpio resetVinod Koul1-0/+3
Add the reset-gpio for UFS for sm8150-mtp. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200106070826.147064-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-06arm64: dts: hi3798cv200-poplar: add linux,rc-map-name for IRShawn Guo1-0/+1
It adds remote control map name for IR device, so that key event can be reported. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-01-04arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEMNiklas Cassel1-0/+1
Enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191129213917.1301110-6-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: defconfig: enable CONFIG_QCOM_CPRNiklas Cassel1-0/+1
Enable CONFIG_QCOM_CPR. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191129213917.1301110-5-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add CPR and populate OPP tableNiklas Cassel1-8/+124
Add CPR and populate OPP table. Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191129213917.1301110-4-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: defconfig: Enable HFPLLJorge Ramirez-Ortiz1-0/+1
The high frequency pll is required on compatible Qualcomm SoCs to support the CPU frequency scaling feature. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-6-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add DVFS supportJorge Ramirez-Ortiz1-0/+30
Support dynamic voltage and frequency scaling on qcs404. CPUFreq will soon be superseded by Core Power Reduction (CPR, a form of Adaptive Voltage Scaling found on some Qualcomm SoCs like the qcs404). Due to the CPR upstreaming already being in progress - and some commits already merged - the following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-5-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add the clocks for APCS mux/dividerJorge Ramirez-Ortiz1-0/+3
Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-4-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: qcs404: Add HFPLL nodeJorge Ramirez-Ortiz1-0/+9
The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-3-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/dividerJorge Ramirez-Ortiz1-1/+2
Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. The driver still supports the previous bindings; however with this update it we allow the msm8916 to access the parent clock names required by the driver operation using the device tree node. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191125142511.681149-2-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04arm64: dts: qcom: sc7180: Add rpmh power-domain nodeSibi Sankar1-0/+55
Add the DT node for the rpmhpd power controller on SC7180 SoCs. Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191220064823.6115-3-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04mm/memory_hotplug: shrink zones when offlining memoryDavid Hildenbrand1-3/+1
We currently try to shrink a single zone when removing memory. We use the zone of the first page of the memory we are removing. If that memmap was never initialized (e.g., memory was never onlined), we will read garbage and can trigger kernel BUGs (due to a stale pointer): BUG: unable to handle page fault for address: 000000000000353d #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP PTI CPU: 1 PID: 7 Comm: kworker/u8:0 Not tainted 5.3.0-rc5-next-20190820+ #317 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.12.1-0-ga5cab58e9a3f-prebuilt.qemu.4 Workqueue: kacpi_hotplug acpi_hotplug_work_fn RIP: 0010:clear_zone_contiguous+0x5/0x10 Code: 48 89 c6 48 89 c3 e8 2a fe ff ff 48 85 c0 75 cf 5b 5d c3 c6 85 fd 05 00 00 01 5b 5d c3 0f 1f 840 RSP: 0018:ffffad2400043c98 EFLAGS: 00010246 RAX: 0000000000000000 RBX: 0000000200000000 RCX: 0000000000000000 RDX: 0000000000200000 RSI: 0000000000140000 RDI: 0000000000002f40 RBP: 0000000140000000 R08: 0000000000000000 R09: 0000000000000001 R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000140000 R13: 0000000000140000 R14: 0000000000002f40 R15: ffff9e3e7aff3680 FS: 0000000000000000(0000) GS:ffff9e3e7bb00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000000000000353d CR3: 0000000058610000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __remove_pages+0x4b/0x640 arch_remove_memory+0x63/0x8d try_remove_memory+0xdb/0x130 __remove_memory+0xa/0x11 acpi_memory_device_remove+0x70/0x100 acpi_bus_trim+0x55/0x90 acpi_device_hotplug+0x227/0x3a0 acpi_hotplug_work_fn+0x1a/0x30 process_one_work+0x221/0x550 worker_thread+0x50/0x3b0 kthread+0x105/0x140 ret_from_fork+0x3a/0x50 Modules linked in: CR2: 000000000000353d Instead, shrink the zones when offlining memory or when onlining failed. Introduce and use remove_pfn_range_from_zone(() for that. We now properly shrink the zones, even if we have DIMMs whereby - Some memory blocks fall into no zone (never onlined) - Some memory blocks fall into multiple zones (offlined+re-onlined) - Multiple memory blocks that fall into different zones Drop the zone parameter (with a potential dubious value) from __remove_pages() and __remove_section(). Link: http://lkml.kernel.org/r/20191006085646.5768-6-david@redhat.com Fixes: f1dd2cd13c4b ("mm, memory_hotplug: do not associate hotadded memory to zones until online") [visible after d0dc12e86b319] Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Oscar Salvador <osalvador@suse.de> Cc: Michal Hocko <mhocko@suse.com> Cc: "Matthew Wilcox (Oracle)" <willy@infradead.org> Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> Cc: Pavel Tatashin <pasha.tatashin@soleen.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Logan Gunthorpe <logang@deltatee.com> Cc: <stable@vger.kernel.org> [5.0+] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-01-03arm64: dts: pm8004: Add SPMI regulator and add phandles to lsidsAngeloGioacchino Del Regno1-2/+8
Add the SPMI regulator node in the PM8004 LSID5 (as there is where it resides basically 99% of the times) and set the nodes to be disabled by default, as not all boards have both or one of the lsids specified in this generic pm8004 DT. While at it, also add nice phandles to the lsids specified in this DT to allow configuration in specific board dts in a more human readable fashion. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lore.kernel.org/r/20191031111645.34777-3-kholk11@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-03compat: provide compat_ptr() on all architecturesArnd Bergmann1-17/+0
In order to avoid needless #ifdef CONFIG_COMPAT checks, move the compat_ptr() definition to linux/compat.h where it can be seen by any file regardless of the architecture. Only s390 needs a special definition, this can use the self-#define trick we have elsewhere. Reviewed-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-01-03compat: ARM64: always include asm-generic/compat.hArnd Bergmann1-2/+3
In order to use compat_* type defininitions in device drivers outside of CONFIG_COMPAT, move the inclusion of asm-generic/compat.h ahead of the #ifdef. All other architectures already do this. Acked-by: Will Deacon <will@kernel.org> Reviewed-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-01-02arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916Ulf Hansson1-4/+53
To enable the OS to better support PSCI OS initiated CPU suspend mode, let's convert from the flattened layout to the hierarchical layout. In the hierarchical layout, let's create a power domain provider per CPU and describe the idle states for each CPU inside the power domain provider node. To group the CPUs into a cluster, let's add another power domain provider and make it act as the master domain. Note that, the CPU's idle states remains compatible with "arm,idle-state", while the cluster's idle state becomes compatible with "domain-idle-state". Co-developed-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
2019-12-31arm64: dts: rockchip: Add RK3328 idle stateRobin Murphy1-0/+17
Downstream RK3328 DTBs describe a CPU idle state matching that present on other SoCs like RK3399. This works with upstream Trusted Firmware-A too, so let's add it here. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/a8c83e705d387446ea8121516d410e38b2d9c57b.1577640736.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-12-31arm64: dts: rockchip: remove identical &uart0 node from rk3368-lion-haikouJohan Jonker1-6/+0
There are two identical &uart0 nodes in this dts file, so remove one of them. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20191228074757.2075-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-12-31arm64: dts: renesas: Prepare for split of ARCH_R8A7795 into ARCH_R8A7795[01]Geert Uytterhoeven1-0/+4
As R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, CONFIG_ARCH_R8A7795 will be split in CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951. Relax dependencies by handling both the old and the new symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191217183841.432-5-geert+renesas@glider.be
2019-12-31arm64: dts: renesas: Sort DTBs in MakefileGeert Uytterhoeven1-10/+7
Sort the entries for the various DTBs in the Makefile by SoC and board type. Keep Salvator-X(S) together, and do the same for ULCB with and without Kingfisher extension. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191217183841.432-4-geert+renesas@glider.be
2019-12-31arm64: dts: renesas: Drop redundant SoC prefixes from ULCB DTS file namesGeert Uytterhoeven9-12/+12
Unlike the V3MSK and V3HSK boards, the various "ULCB" boards are really the same boards, with different SiPs fitted, just like the Salvator-X(S) boards. Furthermore, the "H3", "M3", and "M3N" prefixes of the "ULCB" parts in the DTS file names are redundant, as they are implied by the SoC part numbers, which are also part of the file names. Hence drop the redundant prefixes, to make the DTS file names consistent with the file names for the various "Salvator-X(S)" boards. Suggested-by: Eugeniu Rosca <erosca@de.adit-jv.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191217183841.432-3-geert+renesas@glider.be
2019-12-31arm64: dts: renesas: Rename r8a7795{-es1,}* to r8a7795[01]*Geert Uytterhoeven10-24/+24
Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers. Reflect this in the DTS files by changing their base names from "r8a7795-es1" and "r8a7795" to "r8a77950" resp. "r8a77951". Drop all "ES" references next to part numbers, as they are implied by the part numbers, and thus redundant. Note that DT binding headers, definitions, and compatible values are not renamed, to preserve backward compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191217183841.432-2-geert+renesas@glider.be
2019-12-28arm64: dts: msm8998: thermal: Add critical interrupt supportAmit Kucheria1-4/+6
Register critical interrupts for each of the two tsens controllers Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/3ef309a98ca6445c1982ec3ff1a70db39b18f415.1575349416.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-28arm64: dts: msm8996: thermal: Add critical interrupt supportAmit Kucheria1-4/+6
Register critical interrupts for each of the two tsens controllers Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/53d8f7b922ec889ed11380896c2a367ae0998db2.1575349416.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-27Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-nextDavid S. Miller1-0/+1
Daniel Borkmann says: ==================== pull-request: bpf-next 2019-12-27 The following pull-request contains BPF updates for your *net-next* tree. We've added 127 non-merge commits during the last 17 day(s) which contain a total of 110 files changed, 6901 insertions(+), 2721 deletions(-). There are three merge conflicts. Conflicts and resolution looks as follows: 1) Merge conflict in net/bpf/test_run.c: There was a tree-wide cleanup c593642c8be0 ("treewide: Use sizeof_field() macro") which gets in the way with b590cb5f802d ("bpf: Switch to offsetofend in BPF_PROG_TEST_RUN"): <<<<<<< HEAD if (!range_is_zero(__skb, offsetof(struct __sk_buff, priority) + sizeof_field(struct __sk_buff, priority), ======= if (!range_is_zero(__skb, offsetofend(struct __sk_buff, priority), >>>>>>> 7c8dce4b166113743adad131b5a24c4acc12f92c There are a few occasions that look similar to this. Always take the chunk with offsetofend(). Note that there is one where the fields differ in here: <<<<<<< HEAD if (!range_is_zero(__skb, offsetof(struct __sk_buff, tstamp) + sizeof_field(struct __sk_buff, tstamp), ======= if (!range_is_zero(__skb, offsetofend(struct __sk_buff, gso_segs), >>>>>>> 7c8dce4b166113743adad131b5a24c4acc12f92c Just take the one with offsetofend() /and/ gso_segs. Latter is correct due to 850a88cc4096 ("bpf: Expose __sk_buff wire_len/gso_segs to BPF_PROG_TEST_RUN"). 2) Merge conflict in arch/riscv/net/bpf_jit_comp.c: (I'm keeping Bjorn in Cc here for a double-check in case I got it wrong.) <<<<<<< HEAD if (is_13b_check(off, insn)) return -1; emit(rv_blt(tcc, RV_REG_ZERO, off >> 1), ctx); ======= emit_branch(BPF_JSLT, RV_REG_T1, RV_REG_ZERO, off, ctx); >>>>>>> 7c8dce4b166113743adad131b5a24c4acc12f92c Result should look like: emit_branch(BPF_JSLT, tcc, RV_REG_ZERO, off, ctx); 3) Merge conflict in arch/riscv/include/asm/pgtable.h: <<<<<<< HEAD ======= #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) #define VMALLOC_END (PAGE_OFFSET - 1) #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) #define BPF_JIT_REGION_SIZE (SZ_128M) #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) #define BPF_JIT_REGION_END (VMALLOC_END) /* * Roughly size the vmemmap space to be large enough to fit enough * struct pages to map half the virtual address space. Then * position vmemmap directly below the VMALLOC region. */ #define VMEMMAP_SHIFT \ (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) #define VMEMMAP_END (VMALLOC_START - 1) #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) #define vmemmap ((struct page *)VMEMMAP_START) >>>>>>> 7c8dce4b166113743adad131b5a24c4acc12f92c Only take the BPF_* defines from there and move them higher up in the same file. Remove the rest from the chunk. The VMALLOC_* etc defines got moved via 01f52e16b868 ("riscv: define vmemmap before pfn_to_page calls"). Result: [...] #define __S101 PAGE_READ_EXEC #define __S110 PAGE_SHARED_EXEC #define __S111 PAGE_SHARED_EXEC #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) #define VMALLOC_END (PAGE_OFFSET - 1) #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) #define BPF_JIT_REGION_SIZE (SZ_128M) #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) #define BPF_JIT_REGION_END (VMALLOC_END) /* * Roughly size the vmemmap space to be large enough to fit enough * struct pages to map half the virtual address space. Then * position vmemmap directly below the VMALLOC region. */ #define VMEMMAP_SHIFT \ (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) #define VMEMMAP_END (VMALLOC_START - 1) #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) [...] Let me know if there are any other issues. Anyway, the main changes are: 1) Extend bpftool to produce a struct (aka "skeleton") tailored and specific to a provided BPF object file. This provides an alternative, simplified API compared to standard libbpf interaction. Also, add libbpf extern variable resolution for .kconfig section to import Kconfig data, from Andrii Nakryiko. 2) Add BPF dispatcher for XDP which is a mechanism to avoid indirect calls by generating a branch funnel as discussed back in bpfconf'19 at LSF/MM. Also, add various BPF riscv JIT improvements, from Björn Töpel. 3) Extend bpftool to allow matching BPF programs and maps by name, from Paul Chaignon. 4) Support for replacing cgroup BPF programs attached with BPF_F_ALLOW_MULTI flag for allowing updates without service interruption, from Andrey Ignatov. 5) Cleanup and simplification of ring access functions for AF_XDP with a bonus of 0-5% performance improvement, from Magnus Karlsson. 6) Enable BPF JITs for x86-64 and arm64 by default. Also, final version of audit support for BPF, from Daniel Borkmann and latter with Jiri Olsa. 7) Move and extend test_select_reuseport into BPF program tests under BPF selftests, from Jakub Sitnicki. 8) Various BPF sample improvements for xdpsock for customizing parameters to set up and benchmark AF_XDP, from Jay Jayatheerthan. 9) Improve libbpf to provide a ulimit hint on permission denied errors. Also change XDP sample programs to attach in driver mode by default, from Toke Høiland-Jørgensen. 10) Extend BPF test infrastructure to allow changing skb mark from tc BPF programs, from Nikita V. Shirokov. 11) Optimize prologue code sequence in BPF arm32 JIT, from Russell King. 12) Fix xdp_redirect_cpu BPF sample to manually attach to tracepoints after libbpf conversion, from Jesper Dangaard Brouer. 13) Minor misc improvements from various others. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-12-27arm64: dts: allwinner: h6: Add thermal sensor and thermal zonesOndrej Jirman1-0/+33
There are two sensors, one for CPU, one for GPU. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-26arm64: dts: qcom: db845c: Move remoteproc firmware to sdm845Bjorn Andersson1-2/+7
The redistributable firmware should work on any engineering device, so lets push this to qcom/sdm845, rather than qcom/db845c. Also specify the path for the modem firmware. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191113203951.3704428-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Introduce IFC6640Bjorn Andersson2-0/+386
Introduce a base dts for the Inforce 6640 Single Board Computer. This initial commit boots to console on the uart and provides UFS and SD card storage support. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Use regulator names from schematicsBjorn Andersson1-69/+142
Update the regulator names in db820c.dtsi to use the names from the schematics, instead of the made up genric names. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsiBjorn Andersson1-1433/+1429
Sort all the nodes by unit address, then name. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Pad addressesBjorn Andersson1-72/+72
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it easier to ensure ordering when adding new nodes. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Remove pin specific filesBjorn Andersson3-203/+190
Rather than scattering pinctrl definitions in various files, merge the nodes into db820c.dtsi to make it easier to navigate. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Sort all nodesBjorn Andersson1-168/+168
Sort all nodes in db820c.dtsi based on address, then name. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Group root nodesBjorn Andersson1-49/+45
Prior refactoring have left a few root nodes scattered throughout db820c.dtsi, group these at the top of the file. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Move regulators to db820cBjorn Andersson2-202/+153
As the definition of available PMICs and the names of their outputs are board specifc move this to db820c.dtsi Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Move regulator consumers to db820cBjorn Andersson2-44/+44
Supplies for the various components in the SoC depends on board layout, so move the supply definitions to db820c.dtsi instead of carrying them in the platform dtsi. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: msm8996: Use node references in db820cBjorn Andersson2-354/+341
Instead of mimicing the structure of the platform, reference nodes by their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where necessary. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26arm64: dts: qcom: db820c: Move non-soc entries out of /socBjorn Andersson1-29/+29
The USB id pins and wlan regulator are not platform devices, so move them out of /soc Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-26ARM: dts: sunxi: Add Libre Computer ALL-H3-IT H5 boardChen-Yu Tsai2-0/+12
The Libre Computer ALL-H3-IT board is a small single board computer that is roughly the same size as the Raspberry Pi Zero, or around 20% smaller than a credit card. The board features: - H2, H3, or H5 SoC from Allwinner - 2 DDR3 DRAM chips - Realtek RTL8821CU based WiFi module - 128 Mbit SPI-NOR flash - micro-SD card slot - micro HDMI video output - FPC connector for camera sensor module - generic Raspberri-Pi style 40 pin GPIO header - additional pin headers for extra USB host ports, ananlog audio and IR receiver Only H5 variant test samples were made available, but the vendor does have plans to include at least an H3 variant. Thus the device tree is split much like the ALL-H3-CC, with a common dtsi file for the board design, and separate dts files including the common board file and the SoC dtsi file. The other variants will be added as they are made available. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-26arm64: dts: allwinner: a64: Add MIPI DSI pipelineJagan Teki1-0/+37
Add MIPI DSI pipeline for Allwinner A64. - dsi node, with A64 compatible since it doesn't support DSI_SCLK gating unlike A33 - dphy node, with A64 compatible with A33 fallback since DPHY on A64 and A33 is similar - finally, attach the dsi_in to tcon0 for complete MIPI DSI Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Merlijn Wajer <merlijn@wizzup.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-26arm64: dts: allwinner: a64: Add thermal sensors and thermal zonesVasily Khoruzhick1-0/+42
A64 has 3 thermal sensors: 1 for CPU, 2 for GPU. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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