aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm64
AgeCommit message (Collapse)AuthorFilesLines
2019-11-04arm64: dts: imx8mq-evk: Add remote controlRogerio Pimentel da Silva1-0/+13
Add remote control to i.MX8M EVK device tree. The rc protocol must be selected by writing to: /sys/devices/platform/ir-receiver/rc/rc0/protocols On my tests, I used "nec" rc protocol: echo nec > protocols Tested using evetest: evtest /dev/input/event0 Output log for each key pressed: Event: time 1568122608.267845, -------------- SYN_REPORT ------------ Event: time 1568122610.503835, type 4 (EV_MSC), code 4 (MSC_SCAN), value 440 Signed-off-by: Rogerio Pimentel da Silva <rpimentel.silva@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-02Merge tag 'arm64_defconfig_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/defconfigOlof Johansson1-0/+3
arm64 defconfig for v5.5 - Add SPI_CADENCE_QUADSPI to support the Cadence QSPI driver - Add INTEL_STRATIX10_RSU as a module to support the Remote Service Update driver on Stratix10 and Agilex platforms - Add GPIO_ALTERA as a module to support the Altera GPIO driver * tag 'arm64_defconfig_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: defconfig: enable Altera GPIO controller arm64: defconfig: enable rsu driver arm64: defconfig: enable the Cadence QSPI controller Link: https://lore.kernel.org/r/20191029143737.24850-2-dinguyen@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-02Merge tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dtOlof Johansson3-2/+92
SoCFPGA DTS updates for v5.5 - Arria10 - modify QSPI read-delay property - Agilex - Add QSPI support - Enable USB and LEDs - Add service layer, fpga manager support - Stratix10 - Update QSPI reg address * tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: add service layer, fpga manager and fpga region arm64: agilex: enable USB and LEDs on agilex devkit arm64: dts: altera: update QSPI reg addresses for Stratix10 arm64: dts: agilex: add QSPI support for Intel Agilex ARM: dts: arria10: Modify QSPI read_delay for Arria10 Link: https://lore.kernel.org/r/20191029143737.24850-1-dinguyen@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-02Merge tag 'imx-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesOlof Johansson3-7/+7
i.MX fixes for 5.4, 2nd round: - Get SNVS power key back to work for imx6-logicpd board. It was accidentally disabled by commit 770856f0da5d ("ARM: dts: imx6qdl: Enable SNVS power key according to board design"). - Fix sparse warnings in IMX GPC driver by making the initializers in imx_gpc_domains C99 format. - Fix an interrupt storm coming from accelerometer on imx6qdl-sabreauto board. This is seen with upstream version U-Boot where pinctrl is not configured for the device. - Fix sdma device compatible string for i.MX8MM and i.MX8MN SoC. - Fix compatible of PCA9547 i2c-mux on LS1028A QDS board to get the device probed correctly. * tag 'imx-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mn: fix compatible string for sdma arm64: dts: imx8mm: fix compatible string for sdma ARM: dts: imx6-logicpd: Re-enable SNVS power key soc: imx: gpc: fix initialiser format ARM: dts: imx6qdl-sabreauto: Fix storm of accelerometer interrupts arm64: dts: ls1028a: fix a compatible issue Link: https://lore.kernel.org/r/20191029110334.GA20928@dragon Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-02arm64: allwinner: h6: Enable GPU node for Tanix TX6Clément Péron1-0/+4
Unlike other H6 boards, Tanix TX6 doesn't have a PMIC so we can enable the GPU without providing a specific power supply. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds3-18/+58
Pull arm64 fixes from Will Deacon: "These are almost exclusively related to CPU errata in CPUs from Broadcom and Qualcomm where the workarounds were either not being enabled when they should have been or enabled when they shouldn't have been. The only "interesting" fix is ensuring that writeable, shared mappings are initially mapped as clean since we inadvertently broke the logic back in v4.14 and then noticed the problem via code inspection the other day. The only critical issue we have outstanding is a sporadic NULL dereference in the scheduler, which doesn't appear to be arm64-specific and PeterZ is tearing his hair out over it at the moment. Summary: - Enable CPU errata workarounds for Broadcom Brahma-B53 - Enable CPU errata workarounds for Qualcomm Hydra/Kryo CPUs - Fix initial dirty status of writeable, shared mappings" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core arm64: Brahma-B53 is SSB and spectre v2 safe arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for Kryo arm64: cpufeature: Enable Qualcomm Falkor/Kryo errata 1003 arm64: Ensure VM_WRITE|VM_SHARED ptes are clean by default
2019-11-01arm64: perf: Simplify the ARMv8 PMUv3 event attributesShaokun Zhang1-125/+66
For each PMU event, there is a ARMV8_EVENT_ATTR(xx, XX) and &armv8_event_attr_xx.attr.attr. Let's redefine the ARMV8_EVENT_ATTR to simplify the armv8_pmuv3_event_attrs. Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> [will: Dropped unnecessary array syntax] Signed-off-by: Will Deacon <will@kernel.org>
2019-11-01arm64: defconfig: Enable R8A77961 SoCGeert Uytterhoeven1-0/+1
Enable the Renesas R-Car M3-W+ (R8A77961) SoC in the ARM64 defconfig. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-11-geert+renesas@glider.be
2019-11-01arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+Geert Uytterhoeven2-0/+32
Add initial support for the Renesas Salvator-X 2nd version development board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM. The memory map is as follows: - Bank0: 4GiB RAM : 0x000048000000 -> 0x000bfffffff 0x000480000000 -> 0x004ffffffff - Bank1: 4GiB RAM : 0x000600000000 -> 0x006ffffffff Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-10-geert+renesas@glider.be
2019-11-01arm64: dts: renesas: Add Renesas R8A77961 SoC supportGeert Uytterhoeven1-0/+723
Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC. This includes: - Cortex-A57 and Cortex-A53 CPU cores (incl. L2 caches and power state definitions), - Power Management Unit, - PSCI firmware, - Pin Function Controller, - Clock, Reset, System, and Interrupt Controllers, - SCIF2 serial console, - Product Register, - ARM Architectured Timer, and various placeholders to allow to use salvator-xs.dtsi. Based on r8a7796.dtsi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-9-geert+renesas@glider.be
2019-11-01arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960Geert Uytterhoeven1-0/+3
CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961. Relax dependencies by handling both symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-8-geert+renesas@glider.be
2019-11-01arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 coreFlorian Fainelli1-3/+20
The Broadcom Brahma-B53 core is susceptible to the issue described by ARM64_ERRATUM_843419 so this commit enables the workaround to be applied when executing on that core. Since there are now multiple entries to match, we must convert the existing ARM64_ERRATUM_843419 into an erratum list and use cpucap_multi_entry_cap_matches to match our entries. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Will Deacon <will@kernel.org>
2019-11-01arm64: Brahma-B53 is SSB and spectre v2 safeFlorian Fainelli1-0/+2
Add the Brahma-B53 CPU (all versions) to the whitelists of CPUs for the SSB and spectre v2 mitigations. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Will Deacon <will@kernel.org>
2019-11-01arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 coreDoug Berger2-2/+13
The Broadcom Brahma-B53 core is susceptible to the issue described by ARM64_ERRATUM_845719 so this commit enables the workaround to be applied when executing on that core. Since there are now multiple entries to match, we must convert the existing ARM64_ERRATUM_845719 into an erratum list. Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Will Deacon <will@kernel.org>
2019-11-01dma/direct: turn ARCH_ZONE_DMA_BITS into a variableNicolas Saenz Julienne2-4/+7
Some architectures, notably ARM, are interested in tweaking this depending on their runtime DMA addressing limitations. Acked-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-11-01arm64: dts: allwinner: bluetooth for Emlid Neutis N5Georgii Staroselskii1-0/+13
The Emlid Neutis N5 board has AP6212 BT+WiFi chip. This patch is in line with 8558c6e21ceb ("ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board") and other commits that add Bluetooth support for similar boards. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: defconfig: add new Allwinner crypto optionsCorentin Labbe1-0/+2
This patch adds the new allwinner crypto configs to ARM64 defconfig Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. This patch enables the Crypto Engine on the Allwinner H6 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add crypto engine node on H5Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H5 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01crypto: skcipher - rename the crypto_blkcipher module and kconfig optionEric Biggers1-4/+4
Now that the blkcipher algorithm type has been removed in favor of skcipher, rename the crypto_blkcipher kernel module to crypto_skcipher, and rename the config options accordingly: CONFIG_CRYPTO_BLKCIPHER => CONFIG_CRYPTO_SKCIPHER CONFIG_CRYPTO_BLKCIPHER2 => CONFIG_CRYPTO_SKCIPHER2 Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-11-01crypto: arm64/aes-neonbs - add return value of skcipher_walk_done() in __xts_crypt()Yunfeng Ye1-1/+1
A warning is found by the static code analysis tool: "Identical condition 'err', second condition is always false" Fix this by adding return value of skcipher_walk_done(). Fixes: 67cfa5d3b721 ("crypto: arm64/aes-neonbs - implement ciphertext stealing for XTS") Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-10-31arm64: dts: qcom: msm8998: Disable coresight by defaultSai Prakash Ranjan2-17/+102
Boot failure has been reported on MSM8998 based laptop when coresight is enabled. This is most likely due to lack of firmware support for coresight on production device when compared to debug device like MTP where this issue is not observed. So disable coresight by default for MSM8998 and enable it only for MSM8998 MTP. Reported-and-tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support") Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-31arm64: dts: qcom: msm8998-clamshell: Remove retention idle stateJeffrey Hugo1-0/+37
The retention idle state does not appear to be supported by the firmware present on the msm8998 laptops since the state is advertised as disabled in ACPI, and attempting to enable the state in DT is observed to result in boot hangs. Therefore, remove the state from use to address the observed issues. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Fixes: 2c6d2d3a580a (arm64: dts: qcom: Add Lenovo Miix 630) Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-31arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for KryoBjorn Andersson1-6/+14
The Kryo cores share errata 1009 with Falkor, so add their model definitions and enable it for them as well. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [will: Update entry in silicon-errata.rst] Signed-off-by: Will Deacon <will@kernel.org>
2019-10-31arm64: dts: allwinner: Add mali GPU supply for H6 boardsClément Péron4-0/+24
Enable and add supply to the Mali GPU node on all the H6 boards. Regarding the datasheet the maximum time for supply to reach its voltage is 32ms. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-31arm64: dts: allwinner: Add ARM Mali GPU node for H6Clément Péron1-0/+14
Add the mali gpu node to the H6 device-tree. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-29arm64: tegra: Add Jetson Nano SC7 timingsSowjanya Komatineni1-0/+7
Add platform specific SC7 timing configuration to the Jetson Nano device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add Jetson TX1 SC7 timingsSowjanya Komatineni1-0/+7
Add platform specific SC7 timing configuration to the Jetson TX1 device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable wake from deep sleep on RTC alarmSowjanya Komatineni1-1/+4
This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add PMU on Tegra210Thierry Reding1-0/+10
The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather statistics about the processors and their memory system. Add a device tree node so that this functionality can be exposed. Reported-by: William Cohen <giantklein@gmail.com> Tested-by: William Cohen <giantklein@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add blank lines for better readabilityThierry Reding1-0/+3
Separate the individual thermal zones by a blank line for improved readability. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable DisplayPort on Jetson AGX XavierThierry Reding1-0/+29
Enable both USB-C/DP ports on Jetson AGX Xavier and wire up the power supplies for the SORs that drive these outputs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: p2888: Rename regulators for consistencyThierry Reding1-6/+6
Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the hardware documentation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable DP support on Jetson TX2Thierry Reding1-2/+6
If equipped with an E3320 display module, Jetson TX2 can support DisplayPort. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix compatible for SOR1Thierry Reding1-1/+1
It turns out that both SORs on Tegra186 are the same, so there's no need to distinguish between them in the compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable DP support on Jetson NanoThierry Reding1-0/+28
Add the AVDD_IO_EDP_1V05 and enable the SOR and DPAUX hardware blocks that are used to drive DisplayPort on Jetson Nano. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add SOR0_OUT clock on Tegra210Thierry Reding1-1/+2
This clock was not previously used because it is a fixed clock. However, adding it here allows operating systems to deal with SOR0 the same way as SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Assume no CLKREQ presence by defaultVidya Sagar1-6/+0
Although Tegra194 has support for CLKREQ sideband signal and P2972 has routing of the same till the slot, it is the case most of the time that the connected device doesn't have CLKREQ support. Hence, it makes sense to assume that there is no CLKREQ support by default and it can be enabled on need basis when a card with CLKREQ support is connected. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable SMMU for VIC on Tegra186Thierry Reding1-0/+1
Enable address translation for VIC via the SMMU on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable XUSB host controller on Jetson TX2Nagarjuna Kristam1-1/+1
This enables the use of the USB ports found on the Jetson TX2 for input or external storage, for example. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable SMMU for XUSB host on Tegra186Nagarjuna Kristam1-0/+1
Enabling the SMMU for XUSB host allows buffers to be mapped through the ARM SMMU, which helps protecting the system from rogue memory accesses by the XUSB host. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Enable XUSB pad controller on Jetson TX2Nagarjuna Kristam1-1/+1
The XUSB pad controller is a prerequisite for enabling XUSB support. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add ethernet alias on Jetson AGX XavierThierry Reding1-0/+1
The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that. Generic bootloader code can use this to find the primary Ethernet device and set the MAC address, for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix compatible string for EQOS on Tegra194Thierry Reding1-1/+2
The EQOS Ethernet controller found on Tegra194 is compatible with its predecessor or Tegra186. However, it is an established practice to add a compatible string for the most recent generation of the SoC as well, just in case some incompatibilities or bugs are later discovered. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERMThierry Reding1-1/+3
For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix base address for SOR1 on Tegra194Thierry Reding1-1/+1
The SOR1 hardware block's registers start at physical address 0x15b40000 as correctly specified by the unit-address, but the reg property lists a wrong value, likely because it was copy-and-pasted from SOR0 but not correctly updated. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add unit-address for ACONNECT on Tegra194Thierry Reding2-2/+2
The ACONNECT complex starts at physical address 0x2900000, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add unit-address for CBB on Tegra194Thierry Reding3-12/+12
The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add CPU and cache topology for Tegra194Thierry Reding1-12/+144
Tegra194 has four CPU clusters, each with their own cache hierarchy. This patch creates the CPU map for these clusters and adds the second- and third-level caches and associates them with the CPUs. Signed-off-by: Thierry Reding <treding@nvidia.com>
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.