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2019-10-10arm64: dts: renesas: r8a774b1: Add RWDT nodeFabrizio Castro1-1/+6
Populate the device tree node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G2N (r8a774b1) SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Link: https://lore.kernel.org/r/1570178133-21532-5-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: Add support for Advantech idk-1110wr LVDS panelBiju Das1-0/+41
This patch adds support for Advantech idk-1110wr LVDS panel. The HiHope RZ/G2[MN] is advertised as compatible with panel idk-1110wr from Advantech, however the panel isn't sold alongside the board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-10-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: hihope-rzg2-ex: Add LVDS supportBiju Das1-0/+29
This patch adds LVDS support for RZ/G2[MN] boards. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-9-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: hihope-rzg2-ex: Enable backlightBiju Das1-0/+20
This patch enables backlight support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-8-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add PWM device nodesBiju Das1-0/+70
This patch adds PWM device nodes to r8a774b1 SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-7-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add FDP1 device nodesBiju Das1-0/+10
The r8a774b1 has a single FDP1 instance. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-6-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1-hihope-rzg2n: Add display clock propertiesBiju Das1-0/+11
Add display clock properties for the HiHope RZ/G2N board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-5-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add HDMI encoder instanceBiju Das1-0/+15
Add the HDMI encoder to the R8A774B1 DT in disabled state. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-4-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add DU device to DTBiju Das1-0/+38
Add the DU device to r8a774b1 SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-3-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: hihope-common: Move du clk properties out of common dtsiBiju Das2-8/+11
RZ/G2N board is pin compatible with RZ/G2M board. However on the SoC side RZ/G2N uses DU3 where as RZ/G2M uses DU2 for the DPAD. In order to reuse the common dtsi for both the boards, it is required to move du clock properties from common dtsi to board specific dts. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1570029619-43238-2-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Connect Ethernet-AVB to IPMMU-DS0Biju Das1-0/+1
Add IPMMU-DS0 to the Ethernet-AVB device node. Based on work by Magnus Damm for the r8a7795. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-8-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Tie SYS-DMAC to IPMMU-DS0/1Biju Das1-0/+24
Hook up r8a774b1 DMAC nodes to the IPMMUs. In particular SYS-DMAC0 gets tied to IPMMU-DS0, and SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1. Based on work for the r8a7796 by Magnus Damm. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-7-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add VSP instancesBiju Das1-0/+44
The r8a774b1 has 4 VSP instances. Based on the work done for r8a77965 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-6-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add FCPF and FCPV instancesBiju Das1-0/+40
Add FCPF and FCPV instances to the r8a774b1 dtsi. Based on the work done for r8a77965 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-5-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add IPMMU device nodesBiju Das1-0/+73
Add RZ/G2N (R8A774B1) IPMMU nodes. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-4-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add I2C and IIC-DVFS supportBiju Das1-1/+125
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS) devices nodes to the r8a774b1 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-3-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add SDHI supportBiju Das1-4/+32
Add SDHI support for the r8a774b1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569313375-53428-2-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add TMU device nodesBiju Das1-0/+65
This patch adds TMU[01234] device tree nodes to the r8a774b1 SoC specific DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569250648-33857-5-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add CMT device nodesBiju Das1-0/+70
This patch adds the CMT[0123] device tree nodes to the r8a774b1 SoC specific DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569250648-33857-4-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add RZ/G2N thermal supportBiju Das1-0/+74
Add thermal support for R8A774B1 (RZ/G2N) SoC. Based on the work done for r8a77965 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569250648-33857-3-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devicesBiju Das1-0/+24
This patch adds OPPs table for CA57{0,1} cpu devices. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569250648-33857-2-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: Add HiHope RZ/G2N sub board supportBiju Das2-0/+16
The HiHope RZ/G2N sub board sits below the HiHope RZ/G2N main board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569831527-1250-6-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add Ethernet AVB nodeBiju Das1-1/+41
This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569831527-1250-5-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add GPIO device nodesBiju Das1-8/+56
Add GPIO device nodes to the DT of the r8a774b1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569831527-1250-4-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add SCIF and HSCIF nodesBiju Das1-2/+171
Add the device nodes for RZ/G2N SCIF and HSCIF serial ports, including clocks, power domains and DMAs. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569831527-1250-3-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1: Add SYS-DMAC device nodesBiju Das1-0/+102
Add sys-dmac[0-2] device nodes for RZ/G2N (R8A774B1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569831527-1250-2-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774b1-hihope-rzg2n: Enable HS400 modeBiju Das1-0/+4
This patch enables HS400 mode on HiHope RZ/G2N board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1569837778-55874-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-10arm64: dts: renesas: r8a774a1: Remove audio port nodeBiju Das2-22/+9
This patch removes audio port node from SoC device tree and fixes the below dtb warning Warning (unit_address_vs_reg): /soc/sound@ec500000/ports/port@0: node has a unit name, but no reg property Fixes: e2f04248fcd4 ("arm64: dts: renesas: r8a774a1: Add audio support") Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1570200761-884-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-09arm64: dts: msm8916-samsung-a2015: add tactile buttons and hall sensorMichael Srba1-0/+76
Add nodes for basic GPIO connected hardware to the Samsung A3/A5 common dtsi. This includes the Volume UP button, the Home button, and the hall sensor used to sense "smart cover" open state. Related to that, add a node for the Volume DOWN button, which is handled by the pm8916 as is common with msm8916 devices. Tested-by: Stephan Gerhold <stephan@gerhold.net> # a5u Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Michael Srba <Michael.Srba@seznam.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-09Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds14-94/+90
Pull arm64 fixes from Will Deacon: "A larger-than-usual batch of arm64 fixes for -rc3. The bulk of the fixes are dealing with a bunch of issues with the build system from the compat vDSO, which unfortunately led to some significant Makefile rework to manage the horrible combinations of toolchains that we can end up needing to drive simultaneously. We came close to disabling the thing entirely, but Vincenzo was quick to spin up some patches and I ended up picking up most of the bits that were left [*]. Future work will look at disentangling the header files properly. Other than that, we have some important fixes all over, including one papering over the miscompilation fallout from forcing CONFIG_OPTIMIZE_INLINING=y, which I'm still unhappy about. Harumph. We've still got a couple of open issues, so I'm expecting to have some more fixes later this cycle. Summary: - Numerous fixes to the compat vDSO build system, especially when combining gcc and clang - Fix parsing of PAR_EL1 in spurious kernel fault detection - Partial workaround for Neoverse-N1 erratum #1542419 - Fix IRQ priority masking on entry from compat syscalls - Fix advertisment of FRINT HWCAP to userspace - Attempt to workaround inlining breakage with '__always_inline' - Fix accidental freeing of parent SVE state on fork() error path - Add some missing NULL pointer checks in instruction emulation init - Some formatting and comment fixes" [*] Will's final fixes were Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> but they were already in linux-next by then and he didn't rebase just to add those. * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (21 commits) arm64: armv8_deprecated: Checking return value for memory allocation arm64: Kconfig: Make CONFIG_COMPAT_VDSO a proper Kconfig option arm64: vdso32: Rename COMPATCC to CC_COMPAT arm64: vdso32: Pass '--target' option to clang via VDSO_CAFLAGS arm64: vdso32: Don't use KBUILD_CPPFLAGS unconditionally arm64: vdso32: Move definition of COMPATCC into vdso32/Makefile arm64: Default to building compat vDSO with clang when CONFIG_CC_IS_CLANG lib: vdso: Remove CROSS_COMPILE_COMPAT_VDSO arm64: vdso32: Remove jump label config option in Makefile arm64: vdso32: Detect binutils support for dmb ishld arm64: vdso: Remove stale files from old assembly implementation arm64: vdso32: Fix broken compat vDSO build warnings arm64: mm: fix spurious fault detection arm64: ftrace: Ensure synchronisation in PLT setup for Neoverse-N1 #1542419 arm64: Fix incorrect irqflag restore for priority masking for compat arm64: mm: avoid virt_to_phys(init_mm.pgd) arm64: cpufeature: Effectively expose FRINT capability to userspace arm64: Mark functions using explicit register variables as '__always_inline' docs: arm64: Fix indentation and doc formatting arm64/sve: Fix wrong free for task->thread.sve_state ...
2019-10-09arm64: dts: armada-3720-turris-mox: add firmware nodeMarek Behún1-0/+8
Add the node representing the firmware running on the secure processor. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: add ESPRESSObin variantsTomasz Maciej Nowak5-183/+315
This commit adds dts for different variants of ESPRESSObin board: ESPRESSObin with soldered eMMC, ESPRESSObin V7, compared to prior versions some passive elements changed and ethernet ports labels positions have been reversed, ESPRESSObin V7 with soldered eMMC. Since most of elements are the same, one common dtsi is created and referenced in each dts of particular variant. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9132-DBGrzegorz Jaszczyk2-0/+222
Extend the support of the CN9131 with yet another additional CP115. The last number indicates how many external CP115 are used. New available interfaces: * CP2 CRYPTO-0 (disabled) * CP2 ETH-0 (SFI, problem with the SFP cage, disabled) * CP2 GPIO-1 * CP2 GPIO-2 * CP2 I2C-0 * CP2 PCIe-0 x2 * CP2 PCIe-2 x1 (disabled) * CP2 SDHCI-0 * CP2 USB3-1 (High-speed) Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9131-DBGrzegorz Jaszczyk2-0/+203
Extend the support of the CN9130 by adding an external CP115. The last number indicates how many external CP115 are used. New available interfaces: * CP1 CRYPTO-0 (disabled) * CP1 ETH-0 (SFI, problem with the SFP cage, disabled) * CP1 GPIO-1 * CP1 GPIO-2 * CP1 I2C-0 * CP1 PCIe-0 x2 * CP1 SPI-1 * CP1 SATA-0-1 * CP1 USB3-1 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9130-DBGrzegorz Jaszczyk2-0/+404
Add basic support for the Marvell CN9130 modular development board. It is based on a CN9130 SoC (one AP807 and one internal CP115), extended via 2xMoCi interface to possibly add up to two more external CP115 (one located on the main board and the other on the board extension). Available interfaces: * AP UART * AP eMMC * AP SDHCI (disabled) * CPO GPIO-0 * CPO GPIO-1 * CP0 CRYPTO-0 (disabled) * CP0 I2C-0 * CP0 I2C-1 * CP0 SDHCI-0 * CP0 NAND-0 * CP0 SPI-1 * CP0 ETH-0 (SFI with SFP cage not working yet, disabled) * CP0 ETH-1 (RGMII) * CP0 ETH-2 (RGMII) * CP0 SATA-0-1 * CP0 USB3-0 (High-speed only) * CP0 USB3-1 (High-speed only) * CP0 PCIe-0 x4 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9130 SoC supportMiquel Raynal1-0/+37
A CN9130 SoC has one AP807 and one internal CP115. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for CP115Miquel Raynal1-0/+12
Create a DTSI file based on the CP11x one. Differences will be described in the near future. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Externalize PCIe macros from CP11x fileMiquel Raynal3-11/+16
PCIe macros are specific to CP110 and will not fit CP115 constraints. To keep the same way the files are organized, just move some macros out of the CP11x generic file and define them directly in SoC DTSI, instead of defining single addresses in the SoC DTSI and reusing them in macros. In the end: * CP11X_PCIE_MEM_BASE SoC define is dropped * CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the SoC files as it replaces the above definition. * As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with newer SoCs, we put it in the SoC files as well. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Drop PCIe I/O ranges from CP11x fileMiquel Raynal4-21/+4
As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory range. This shows that I/O memory has never been used/working on the old SoCs despite the region being advertised. As PCIe I/O ranges will not be supported in newer SoCs using CP11x co-processors, let's simply drop them. It is not harmful in any case as PCIe device drivers can do it all with the regular mapped memory anyway. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Prepare the introduction of CP115Miquel Raynal5-615/+627
CP110 and CP115 are almost the same in terms of features and have a very limited set of differences. Let's create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115 nodes. The only changes between the two armada-cp11{0,x}.dtsi files are the following naming in macros: s/CP110/CP11X/. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignmentMiquel Raynal1-4/+4
Fix this tiny typo before renaming/changing this file. Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP807-quad cache descriptionGrzegorz Jaszczyk1-0/+42
Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP806-quad cache descriptionGrzegorz Jaszczyk1-0/+42
Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP806-dual cache descriptionGrzegorz Jaszczyk1-0/+21
Adding appropriate entries to device-tree allows the cache description to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for AP807/AP807-quadMiquel Raynal2-0/+80
Describe AP807 and AP807-quad support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Move clocks to AP806 specific fileMiquel Raynal2-12/+16
Regular clocks and CPU clocks are specific to AP806, move them out of the generic AP80x file so that AP807 can use its own clocks. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Prepare the introduction of AP807 based SoCsKonstantin Porotchkin2-446/+458
Prepare the support for Marvell AP807 die. This die is very similar to AP806 but uses different DDR PHY. AP807 is a major component of CN9130 SoC series. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add AP806-dual missing CPU clocksMiquel Raynal1-0/+2
CPU clocks have been added to AP806-quad but not to the -dual variant. Fixes: c00bc38354cf ("arm64: dts: marvell: Add cpu clock node on Armada 7K/8K") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: armada-3720-turris-mox: convert usb-phy to phy-supplyMarek Behún1-6/+7
Update Turris Mox device tree to use the phy-supply property of the generic PHY framework instead of the legacy usb-phy property. This is needed since it caused a regression on Turris Mox since "usb: host: xhci-plat: Prevent an abnormally restrictive PHY init skipping". Signed-off-by: Marek Behún <marek.behun@nic.cz> Fixes: eb6c2eb6c7fb ("usb: host: xhci-plat: Prevent an abnormally restrictive PHY init skipping") Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-08arm64: armv8_deprecated: Checking return value for memory allocationYunfeng Ye1-0/+5
There are no return value checking when using kzalloc() and kcalloc() for memory allocation. so add it. Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com> Signed-off-by: Will Deacon <will@kernel.org>
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