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2019-04-18arm64: dts: allwinner: a64-amarula-relic: Add OV5640 camera nodeJagan Teki1-0/+50
Amarula A64-Relic board by default bound with OV5640 camera, so add support for it with below pin information. - PE13, PE12 via i2c-gpio bitbanging - CLK_CSI_MCLK as external clock - PE1 as external clock pin muxing - ALDO1 as AVDD supply - DLDO3 as DOVDD supply - ELDO3 as DVDD supply - PE14 gpio for reset pin - PE15 gpio for powerdown pin Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1Jagan Teki1-0/+6
Some camera modules have the SoC feeding a master clock to the sensor instead of having a standalone crystal. This clock signal is generated from the clock control unit and output from the CSI MCLK function of pin PE1. Add a pinmux setting for it for camera sensors to reference. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18crypto: arm64/aes-neonbs - don't access already-freed walk.ivEric Biggers1-0/+2
If the user-provided IV needs to be aligned to the algorithm's alignmask, then skcipher_walk_virt() copies the IV into a new aligned buffer walk.iv. But skcipher_walk_virt() can fail afterwards, and then if the caller unconditionally accesses walk.iv, it's a use-after-free. xts-aes-neonbs doesn't set an alignmask, so currently it isn't affected by this despite unconditionally accessing walk.iv. However this is more subtle than desired, and unconditionally accessing walk.iv has caused a real problem in other algorithms. Thus, update xts-aes-neonbs to start checking the return value of skcipher_walk_virt(). Fixes: 1abee99eafab ("crypto: arm64/aes - reimplement bit-sliced ARM/NEON implementation for arm64") Cc: <stable@vger.kernel.org> # v4.11+ Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-04-18mtd: rawnand: Clarify Kconfig entry MTD_NANDMiquel Raynal1-1/+1
MTD_NAND is large and encloses much more than what the symbol is actually used for: raw NAND. Clarify the symbol by naming it MTD_RAW_NAND instead. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-17arm64: dts: allwinner: Fix DE2 bus node nameMaxime Ripard2-2/+2
According to the device tree specification, any bus should have a 'bus' node name. Since it isn't the case for us on the DE2 bus, fix that. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17arm64: tegra: Remove regulator hacks on Jetson TX2Thierry Reding1-23/+0
Various regulators were marked as always-on for Jetson TX2. At this point, all of the regulators are properly hooked up, so this workaround is no longer required. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: tegra: Enable XUSB on P2771Thierry Reding2-4/+130
Enable the relevant pads for XUSB support on P2771-0000 and hook up the USB supply voltage regulators to the ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: tegra: Add XUSB and pad controller on Tegra186Thierry Reding1-0/+135
Adds the XUSB pad and XUSB controllers on Tegra186. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: tegra: Add NVIDIA Jetson Nano Developer Kit supportThierry Reding2-0/+651
The Jetson Nano Developer Kit is a Tegra X1 based development board. It is similar to Jetson TX1 but it is not pin compatible. It features 4 GB of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot used for storage. HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI Ethernet controller provides onboard network connectivity. An M.2 Key-E slot with PCIe x1 adds additional possibilities. A 40-pin header on the board can be used to extend the capabilities and exposed interfaces of the Jetson Nano. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: tegra: smaug: Move PLL power supplies to XUSB pad controllerThierry Reding1-0/+5
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: tegra: jetson-tx1: Move PLL power supplies to XUSB pad controllerThierry Reding1-0/+5
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCIMaxime Ripard3-6/+0
Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16arm64: dts: meson-g12a-u200: Add support for Video DisplayNeil Armstrong1-0/+54
This patch adds the HDMI, CVBS and CEC attributes and nodes to support full display on the U200 Reference Design. AO-CEC-B is used by default and AO-CEC-A is disabled. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16arm64: dts: meson-g12a-sei510: Add support for Video DisplayNeil Armstrong1-0/+53
This patch adds the HDMI, CVBS and CEC attributes and nodes to support full display on the SEI510 STB. AO-CEC-B is used by default and AO-CEC-A is disabled. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16arm64: dts: meson-g12a-x96-max: Add support for Video DisplayNeil Armstrong1-0/+54
This patch adds the HDMI, CVBS and CEC attributes and nodes to support full display on the X96 Max STB. AO-CEC-B is used by default and AO-CEC-A is disabled. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16arm64: dts: meson-g12a: Add AO-CEC nodesNeil Armstrong1-0/+34
Amlogic G12A embeds 2 CEC controllers : - AO-CEC-A the same controller as in GXBB, GXL & GXM SoCs - AO-CEC-B is a new controller Note, the two controller can work simultanously since 2 Pads can handle CEC, thus this SoC can handle 2 distinct CEC busses. This patch adds the nodes for the AO-CEC-A and AO-CEC-B controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16arm64: dts: meson-g12a: Add VPU and HDMI related nodesNeil Armstrong1-0/+131
Add VPU and HDMI display support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16arm64: vdso: Fix clock_getres() for CLOCK_REALTIMEVincenzo Frascino4-5/+8
clock_getres() in the vDSO library has to preserve the same behaviour of posix_get_hrtimer_res(). In particular, posix_get_hrtimer_res() does: sec = 0; ns = hrtimer_resolution; where 'hrtimer_resolution' depends on whether or not high resolution timers are enabled, which is a runtime decision. The vDSO incorrectly returns the constant CLOCK_REALTIME_RES. Fix this by exposing 'hrtimer_resolution' in the vDSO datapage and returning that instead. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> [will: Use WRITE_ONCE(), move adr off COARSE path, renumber labels, use 'w' reg] Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: Use the correct style for SPDX License IdentifierNishad Kamdar4-4/+4
This patch corrects the SPDX License Identifier style in the arm64 Hardware Architecture related files. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: instrument smp_{load_acquire,store_release}Mark Rutland1-9/+15
Our __smp_store_release() and __smp_load_acquire() macros use inline assembly, which is opaque to kasan. This means that kasan can't catch erroneous use of these. This patch adds kasan instrumentation to both. Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> [will: consistently use *p as argument to sizeof] Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: mm: check virtual addr in virt_to_page() if CONFIG_DEBUG_VIRTUAL=yMiles Chen1-1/+1
This change uses the original virt_to_page() (the one with __pa()) to check the given virtual address if CONFIG_DEBUG_VIRTUAL=y. Recently, I worked on a bug: a driver passes a symbol address to dma_map_single() and the virt_to_page() (called by dma_map_single()) does not work for non-linear addresses after commit 9f2875912dac ("arm64: mm: restrict virt_to_page() to the linear mapping"). I tried to trap the bug by enabling CONFIG_DEBUG_VIRTUAL but it did not work - bacause the commit removes the __pa() from virt_to_page() but CONFIG_DEBUG_VIRTUAL checks the virtual address in __pa()/__virt_to_phys(). A simple solution is to use the original virt_to_page() (the one with__pa()) if CONFIG_DEBUG_VIRTUAL=y. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: Advertise ARM64_HAS_DCPODP cpu featureAndrew Murray2-1/+12
Advertise ARM64_HAS_DCPODP when both DC CVAP and DC CVADP are supported. Even though we don't use this feature now, we provide it for consistency with DCPOP and anticipate it being used in the future. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: add CVADP support to the cache maintenance helperAndrew Murray1-0/+4
Allow users of dcache_by_line_op to specify cvadp as an op. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: Expose DC CVADP to userspaceAndrew Murray4-0/+8
ARMv8.5 builds upon the ARMv8.2 DC CVAP instruction by introducing a DC CVADP instruction which cleans the data cache to the point of deep persistence. Let's expose this support via the arm64 ELF hwcaps. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: Handle trapped DC CVADPAndrew Murray2-1/+5
The ARMv8.5 DC CVADP instruction may be trapped to EL1 via SCTLR_EL1.UCI therefore let's provide a handler for it. Just like the CVAP instruction we use a 'sys' instruction instead of the 'dc' alias to avoid build issues with older toolchains. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: HWCAP: encapsulate elf_hwcapAndrew Murray3-17/+38
The introduction of AT_HWCAP2 introduced accessors which ensure that hwcap features are set and tested appropriately. Let's now mandate access to elf_hwcap via these accessors by making elf_hwcap static within cpufeature.c. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: HWCAP: add support for AT_HWCAP2Andrew Murray13-60/+112
As we will exhaust the first 32 bits of AT_HWCAP let's start exposing AT_HWCAP2 to userspace to give us up to 64 caps. Whilst it's possible to use the remaining 32 bits of AT_HWCAP, we prefer to expand into AT_HWCAP2 in order to provide a consistent view to userspace between ILP32 and LP64. However internal to the kernel we prefer to continue to use the full space of elf_hwcap. To reduce complexity and allow for future expansion, we now represent hwcaps in the kernel as ordinals and use a KERNEL_HWCAP_ prefix. This allows us to support automatic feature based module loading for all our hwcaps. We introduce cpu_set_feature to set hwcaps which complements the existing cpu_have_feature helper. These helpers allow us to clean up existing direct uses of elf_hwcap and reduce any future effort required to move beyond 64 caps. For convenience we also introduce cpu_{have,set}_named_feature which makes use of the cpu_feature macro to allow providing a hwcap name without a {KERNEL_}HWCAP_ prefix. Signed-off-by: Andrew Murray <andrew.murray@arm.com> [will: use const_ilog2() and tweak documentation] Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-16arm64: dts: mt8173: add pmu nodes for mt8173Seiya Wang1-0/+14
This patch adds the device nodes of ARM Performance Monitor Uint for mt8173. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-04-16arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72Seiya Wang1-4/+4
The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-04-15arm64: dts: meson-g12a-x96-max: Enable USBNeil Armstrong1-0/+5
Enable the USB2 and USB3 Host ports on the X96 Max Set-Top-Box. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson-g12a-u200: Enable USBNeil Armstrong1-0/+12
Enable the USB2 OTG and USB3 Host ports on the S905D2 Reference Design. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson-g12a-sei510: Enable USBNeil Armstrong1-0/+5
Enable the USB2 and USB3 Host ports on the SEI520 Set-Top-Box. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson-g12a-sei510: Add ADC Key and BT supportNeil Armstrong1-0/+30
Add support for the : - ADC Touch key - Bluetooth Module on UART A Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson-g12a-u200: add regulatorsJerome Brunet1-0/+79
Add system regulators for the S905D U200 reference design. Add some regulators. Still missing * VDD_EE (0.8V - PWM controlled) * VDD_CPU (PWM controlled) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson: g12a: Add mali-g31 gpu nodeNeil Armstrong1-0/+27
This patch adds the ARM Mali G31 GPU node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson: g12a: Add G12A USB nodesNeil Armstrong1-0/+75
This patch adds the nodes for the USB Complex found in the Amlogic G12A SoC. It includes the : - 2 USB2 PHYs - 1 USB3 + PCIE Combo PHY - the USB Glue with it's DWC2 and DWC3 sub-nodes Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: meson: g12a: Add SAR ADC nodeNeil Armstrong1-0/+15
This patch adds the SAR ADC controller node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15arm64: dts: hisilicon: hi3670: Add UFS controller supportManivannan Sadhasivam1-0/+18
Add UFS controller support for HiSilicon HI3670 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-04-15arch: add pidfd and io_uring syscalls everywhereArnd Bergmann2-1/+9
Add the io_uring and pidfd_send_signal system calls to all architectures. These system calls are designed to handle both native and compat tasks, so all entries are the same across architectures, only arm-compat and the generic tale still use an old format. Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> (s390) Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-04-15arm64: dts: renesas: r8a77980: Add "renesas,id" to VINJacopo Mondi1-0/+16
Add the "renesas,id" property to VIN nodes in the R-Car V3H R8A77980 device tree. Fixes: 3182aa4e0bf4 ("arm64: dts: renesas: r8a77980: add CSI2/VIN support") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-15arm64: dts: renesas: r8a77965: Remove reg-names of display nodeTakeshi Kihara1-1/+0
Remove the "reg-names" property from the display node of R-Car Gen3 R8A77965 device tree. No other mainline R-Car Gen3 SoC has that property specified. Fixes: 2f2c71bfc8c5 ("arm64: dts: renesas: r8a77965: Populate the DU instance placeholder") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [reworded commit message, sent upstream] Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-15arm64: dts: allwinner: h6: Add MMC1 pinsOndrej Jirman1-0/+11
MMC1 is used on some H6 boards we want to support. Typical use is 4-bit SDIO interface with a WiFi chip. Add pin definitions for this use case. As this is the only possible configration for mmc1, make it the default one, too. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-14arm64/stacktrace: Remove the pointless ULONG_MAX markerThomas Gleixner1-4/+0
Terminating the last trace entry with ULONG_MAX is a completely pointless exercise and none of the consumers can rely on it because it's inconsistently implemented across architectures. In fact quite some of the callers remove the entry and adjust stack_trace.nr_entries afterwards. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Alexander Potapenko <glider@google.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: https://lkml.kernel.org/r/20190410103644.220247845@linutronix.de
2019-04-12arm64: dts: mt8183: add pinctrl fileZhiyong Tao1-0/+1120
This patch adds pinctrl file for mt8183. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-04-12arm64: dts: Using standard CCF interface to set vcodec clkYunfei Dong1-0/+13
Using standard CCF interface to set vdec/venc parent clk and clk rate. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-04-12arm64: ptrace: Add function argument access APIMasami Hiramatsu2-0/+23
Add regs_get_argument() which returns N th argument of the function call. On arm64, it supports up to 8th argument. Note that this chooses most probably assignment, in some case it can be incorrect (e.g. passing data structure or floating point etc.) This enables ftrace kprobe events to access kernel function arguments via $argN syntax. Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> [will: tidied up the comment a bit] Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-12arm64: tegra: Enable command queue for Tegra186 SDMMC4Sowjanya Komatineni1-0/+1
The workaround for a hardware bug preventing this from working has been merged now, so command queue support can be enabled again for Tegra186. Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Fix default tap and trim valuesSowjanya Komatineni1-2/+2
Default tap and trim values are incorrect for Tegra186 SDMMC4. This patch fixes them. Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Add supply for temperature sensor on P2888Jon Hunter1-0/+1
The VCC supply property is not populated for the temperature sensor on the P2888 board and so the following warning is observed on boot ... lm90 0-004c: 0-004c supply vcc not found, using dummy regulator On the P2888 board, the VCC supply for the temperature sensor is connected to the 'vdd_1v8ls' rail. Add the 'vcc-supply' property for the temperature sensor to prevent this warning message from occurring. Fixes: 8b457812f54b ('arm64: tegra: Add temperature sensor on P2888') Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Enable aconnect, ADMA and AGIC on Jetson TX1Sameer Pujar1-0/+12
These are currently mostly unused because we lack a proper audio driver on Tegra210. However, enabling them makes sure that at least their probe code paths are tested at runtime. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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