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2019-03-20arm64: remove obsolete selection of MULTI_IRQ_HANDLERMatthias Kaehlcke1-1/+0
The arm64 config selects MULTI_IRQ_HANDLER, which was renamed to GENERIC_IRQ_MULTI_HANDLER by commit 4c301f9b6a94 ("ARM: Convert to GENERIC_IRQ_MULTI_HANDLER"). The 'new' option is already selected, so just remove the obsolete entry. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-20arm64: dts: freescale: Enable PCI-E controller for Oxalis boardManivannan Sadhasivam2-1/+5
Enable PCI-E controller for Oxalis board based on NXP/Freescale LS1012a SoC available as the Mini PCI-E connector on the bottom side. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-20arm64: dts: ls1028a: Add pmu dt nodesAlison Wang1-0/+5
This patch adds pmu dt nodes for LS1028A. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-20arm64: dts: imx8mq-evk: Enable audio codec wm8524Daniel Baluta1-0/+48
The main Audio DAC used on the EVK board is wm8524 The EVK provides the MCLK to wm8524. Digital interface is SAI2 which includes three signals: SYNC_CLK, BCLK and DACDAT. This patch sets: * SAI2 pinctrl configuration * clock hierarchy * wm8524 codec Then uses simple-card machine driver to connect them into a sound card. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-20arm64: dts: imx8mq: Add SAI2 nodeDaniel Baluta1-0/+15
SAI2 is part of AIPS-3 memory region. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-20arm64: dts: imx8mq: Add SDMA nodesDaniel Baluta1-0/+22
SDMA1 is part of AIPS-3 region and SDMA2 is part of AIPS-1 region. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19KVM: arm/arm64: vgic-its: Take the srcu lock when writing to guest memoryMarc Zyngier1-0/+11
When halting a guest, QEMU flushes the virtual ITS caches, which amounts to writing to the various tables that the guest has allocated. When doing this, we fail to take the srcu lock, and the kernel shouts loudly if running a lockdep kernel: [ 69.680416] ============================= [ 69.680819] WARNING: suspicious RCU usage [ 69.681526] 5.1.0-rc1-00008-g600025238f51-dirty #18 Not tainted [ 69.682096] ----------------------------- [ 69.682501] ./include/linux/kvm_host.h:605 suspicious rcu_dereference_check() usage! [ 69.683225] [ 69.683225] other info that might help us debug this: [ 69.683225] [ 69.683975] [ 69.683975] rcu_scheduler_active = 2, debug_locks = 1 [ 69.684598] 6 locks held by qemu-system-aar/4097: [ 69.685059] #0: 0000000034196013 (&kvm->lock){+.+.}, at: vgic_its_set_attr+0x244/0x3a0 [ 69.686087] #1: 00000000f2ed935e (&its->its_lock){+.+.}, at: vgic_its_set_attr+0x250/0x3a0 [ 69.686919] #2: 000000005e71ea54 (&vcpu->mutex){+.+.}, at: lock_all_vcpus+0x64/0xd0 [ 69.687698] #3: 00000000c17e548d (&vcpu->mutex){+.+.}, at: lock_all_vcpus+0x64/0xd0 [ 69.688475] #4: 00000000ba386017 (&vcpu->mutex){+.+.}, at: lock_all_vcpus+0x64/0xd0 [ 69.689978] #5: 00000000c2c3c335 (&vcpu->mutex){+.+.}, at: lock_all_vcpus+0x64/0xd0 [ 69.690729] [ 69.690729] stack backtrace: [ 69.691151] CPU: 2 PID: 4097 Comm: qemu-system-aar Not tainted 5.1.0-rc1-00008-g600025238f51-dirty #18 [ 69.691984] Hardware name: rockchip evb_rk3399/evb_rk3399, BIOS 2019.04-rc3-00124-g2feec69fb1 03/15/2019 [ 69.692831] Call trace: [ 69.694072] lockdep_rcu_suspicious+0xcc/0x110 [ 69.694490] gfn_to_memslot+0x174/0x190 [ 69.694853] kvm_write_guest+0x50/0xb0 [ 69.695209] vgic_its_save_tables_v0+0x248/0x330 [ 69.695639] vgic_its_set_attr+0x298/0x3a0 [ 69.696024] kvm_device_ioctl_attr+0x9c/0xd8 [ 69.696424] kvm_device_ioctl+0x8c/0xf8 [ 69.696788] do_vfs_ioctl+0xc8/0x960 [ 69.697128] ksys_ioctl+0x8c/0xa0 [ 69.697445] __arm64_sys_ioctl+0x28/0x38 [ 69.697817] el0_svc_common+0xd8/0x138 [ 69.698173] el0_svc_handler+0x38/0x78 [ 69.698528] el0_svc+0x8/0xc The fix is to obviously take the srcu lock, just like we do on the read side of things since bf308242ab98. One wonders why this wasn't fixed at the same time, but hey... Fixes: bf308242ab98 ("KVM: arm/arm64: VGIC/ITS: protect kvm_read_guest() calls with SRCU lock") Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-03-19KVM: arm64: Reset the PMU in preemptible contextMarc Zyngier1-3/+3
We've become very cautious to now always reset the vcpu when nothing is loaded on the physical CPU. To do so, we now disable preemption and do a kvm_arch_vcpu_put() to make sure we have all the state in memory (and that it won't be loaded behind out back). This now causes issues with resetting the PMU, which calls into perf. Perf itself uses mutexes, which clashes with the lack of preemption. It is worth realizing that the PMU is fully emulated, and that no PMU state is ever loaded on the physical CPU. This means we can perfectly reset the PMU outside of the non-preemptible section. Fixes: e761a927bc9a ("KVM: arm/arm64: Reset the VCPU without preemption and vcpu state loaded") Reported-by: Julien Grall <julien.grall@arm.com> Tested-by: Julien Grall <julien.grall@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-03-19arm64: kpti: Whitelist HiSilicon Taishan v110 CPUsHanjun Guo1-0/+1
HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist the MIDR in kpti_safe_list[] table. Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Reviewed-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: Add MIDR encoding for HiSilicon Taishan CPUsHanjun Guo1-0/+4
Adding the MIDR encodings for HiSilicon Taishan v110 CPUs, which is used in Kunpeng ARM64 server SoCs. TSV110 is the abbreviation of Taishan v110. Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Reviewed-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64/stacktrace: Export save_stack_trace_regs()William Cohen1-0/+1
The ARM64 implements the save_stack_trace_regs function, but it is unusable for any diagnostic tooling compiled as a kernel module due the missing EXPORT_SYMBOL_GPL for the function. Export save_stack_trace_regs() to align with other architectures such as s390, openrisc, and powerpc. This is similar to the ARM64 export of save_stack_trace_tsk() added in git commit e27c7fa015d6. Signed-off-by: William Cohen <wcohen@redhat.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: apply workaround on A64FX v1r0Mark Rutland1-1/+1
Fujitsu erratum 010001 applies to A64FX v0r0 and v1r0, and we try to handle either by masking MIDR with MIDR_FUJITSU_ERRATUM_010001_MASK before comparing it to MIDR_FUJITSU_ERRATUM_010001. Unfortunately, MIDR_FUJITSU_ERRATUM_010001 is constructed incorrectly using MIDR_VARIANT(), which is intended to extract the variant field from MIDR_EL1, rather than generate the field in-place. This results in MIDR_FUJITSU_ERRATUM_010001 being all-ones, and we only match A64FX v0r0. This patch uses MIDR_CPU_VAR_REV() to generate an in-place mask for the variant field, ensuring the we match both v0r0 and v1r0. Fixes: 3e32131abc311a5c ("arm64: Add workaround for Fujitsu A64FX erratum 010001") Reported-by: "Okamoto, Takayuki" <tokamoto@jp.fujitsu.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> [catalin.marinas@arm.com: fixed the patch author] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: dts: imx8mq: add clock for GPIO nodeAnson Huang1-0/+5
i.MX8MQ has clock gate for each GPIO bank, add clock info to GPIO node for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19arm64: kprobes: Use arch_populate_kprobe_blacklist()Masami Hiramatsu1-18/+29
Use arch_populate_kprobe_blacklist() instead of arch_within_kprobe_blacklist() so that we can see the full blacklisted symbols under the debugfs. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> [catalin.marinas@arm.com: Add arch_populate_kprobe_blacklist() comment] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: kprobes: Move exception_text check in blacklistMasami Hiramatsu1-4/+2
Move exception/irqentry text address check in blacklist, since those are symbol based rejection. If we prohibit probing on the symbols in exception_text, those should be blacklisted. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: kprobes: Remove unneeded RODATA checkMasami Hiramatsu1-6/+0
Remove unneeded RODATA check from arch_prepare_kprobe(). Since check_kprobe_address_safe() already ensured that the probe address is in kernel text, we don't need to check whether the address in RODATA or not. That must be always false. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: kprobes: Move extable address check into arch_prepare_kprobe()Masami Hiramatsu1-2/+5
Move extable address check into arch_prepare_kprobe() from arch_within_kprobe_blacklist(). The blacklist is exposed via debugfs as a list of symbols. The extable entries are smaller, so must be filtered out by arch_prepare_kprobe(). Acked-by: Will Deacon <will.deacon@arm.com> Reviewed-by: James Morse <james.morse@arm.com> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-03-19arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodesFabrizio Castro1-4/+8
According to the latest information, clkp2 is available on RZ/G2. Modify CAN0 and CAN1 nodes accordingly. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-19arm64: dts: renesas: r8a774c0: Add CANFD supportFabrizio Castro1-0/+25
The CANFD implementation on the RZ/G2E (a.k.a. r8a774c0) is identical to the one found on the r8a77990. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-19arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodesFabrizio Castro1-4/+8
According to the latest information, clkp2 is available on RZ/G2. Modify CAN0 and CAN1 nodes accordingly. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-19arm64: dts: allwinner: h6: Add Video Engine nodeJernej Skrabec1-0/+11
This adds the Video engine node for H6. It can use whole DRAM range so there is no need for reserved memory node. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-19arm64: dts: imx8mq: Add the opp table and cores opp propertiesAbel Vesa1-0/+23
Add the 0.8GHz and 1GHz opps. According to the datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf section 3.1.3 Operating ranges. The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. The 1GHz runs in overdrive mode with the regulator set to 1V. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19arm64: dts: imx8mq: Add the buck vdd_arm regulatorAbel Vesa1-0/+35
According to the schematics, this is a MP2147 switch converter which is controlled by GPIO1_IO13. When set the gpio is set to high the regulator output is set to 0.9V. When the gpio is set to low the regulator output is set to 1V. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19arm64: dts: imx8mq: Add the clocks and the latencies for the A53 coresAbel Vesa1-0/+8
The clocks and their latencies will be used by cpufreq-dt. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19arm64: dts: ls1028a: Add Audio DT nodesAlison Wang3-0/+182
This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19arm64: dts: imx8mq: Add on-chip OTP controller nodeCarlo Caione1-0/+8
Add the node for the OTP controller. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19arm64: dts: imx8qxp: add cpu opp tableAnson Huang1-0/+30
Add i.MX8QXP CPU opp table to support cpufreq. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-18Merge tag 'tags/bcm2835-drivers-next-2019-03-12' into soc/fixesFlorian Fainelli1-0/+1
This pull request brings in a build fix for arm64 with bcm2835 enabled, and fixes the driver in the presence of -EPROBE_DEFER. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-03-18arm64: dts: meson-gxm-nexbox-a1: Enable USBNeil Armstrong1-0/+4
Enable USB on the Nexbox A1 STB Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18arm64: dts: meson: g12a: add efuseJerome Brunet1-0/+9
Add the g12a SoC efuse device Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18arm64: dts: meson: g12a: add secure monitorJerome Brunet1-0/+4
Add the interface to the secure monitor on g12a Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18arm64: dts: meson-gxl-s905d-phicomm-n1: add status LEDChuanhong Guo1-0/+10
There is a white LED on the front panel behind the logo and the manufacturer uses that LED to indicate network and USB drive status. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18arm64: dts: meson-g12a: Add AO Secure nodeNeil Armstrong1-0/+6
This adds the Always-On ao-secure system control registers node, which is used by the meson-gx-socinfo driver to detect the SoC IDs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18arm64: dts: Add SEI Robotics SEI510 BoardNeil Armstrong2-0/+39
The SEI Robotics SEI510 Board is based on the Amlogic G12A S905X2 and has the following features : - Amlogic G12A S905X2 SoC - 10/100 Ethernet - USB2 + USB3 ports - Micro SDCard Port - Audio + CVBS AV Jack port - HDMI 2.1 + CEC Port - ADC Touch Button - Far-Field Microphone Array + Mono HP - IR Sensor - IR Emmiter LED Array - RGB Led Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: sorted Makefile entry alphabetcially] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-03-18arm64: zynqmp: dt: Add TI PHY quirkHarini Katakam6-0/+6
Add TI PHY strap ctrl quirk for all the HW where applicable. Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-03-18arm64: dts: renesas: ebisu: Add PMIC DDR0 Backup Power configSimon Horman1-0/+2
On Ebisu the DDR0 power rail needs to be kept powered when backup mode is enabled. Reflect this in the "rohm,ddr-backup-power" property for the BD9571MWV PMIC node. The accessory power switch (SW23) is a toggle switch, hence specify "rohm,rstbmode-level". Based on advice from Geert Uytterhoeven. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-03-18arm64: dts: renesas: r8a77990-ebisu: Add BD9571 PMICTakeshi Kihara1-0/+25
This patch adds the regulator definition required for operation of S2RAM. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-03-18arm64: dts: renesas: r8a77990: Remove invalid compatible value for CSI40Niklas Söderlund1-1/+1
The compatible value renesas,rcar-gen3-csi2 was used while prototyping the R-Car CSI-2 driver but was removed before the driver was merged. Remove the only occurrence of the compatible value which manage to make it upstream. Fixes: ec70407ae7d7 ("arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a774c0: Remove invalid compatible value for CSI40Niklas Söderlund1-2/+1
The compatible value renesas,rcar-gen3-csi2 was used while prototyping the R-Car CSI-2 driver but was removed before the driver was merged. Fixes: e961ab42e034d469 ("arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a77995: draak: Enable CAN0, CAN1Marek Vasut1-0/+22
Enable both CAN0 and CAN1 controllers on R8A77995 Draak board, since they are available on connectors CN43, CN44 respectively. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a774c0-cat874: Add RWDT supportFabrizio Castro1-0/+5
Enable RWDT and use 60 seconds as default timeout. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: ebisu: Enable VIN5Takeshi Kihara1-0/+4
Both VIN4 and VIN5 are connected to CSI40 and can be configured at runtime to use the single video source connected to CSI40. Enable VIN5 to allow it to be used in this fashion. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Niklas: rewrite commit message] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a774c0-cat874: Add LEDs supportFabrizio Castro1-0/+24
This patch adds LEDs support to the CAT874 board specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a774c0-cat874: add RTC supportBiju Das1-0/+18
This patch adds Epson RX-8571 real time clock support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: cat875: Add CAN supportFabrizio Castro1-0/+22
Add CAN support to the CAT875 sub board. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a774c0: Fix cpu nodes styleFabrizio Castro1-2/+2
We usually leave a space between "=" and the value of device tree properties, but unfortunately that was overlooked for the "clocks" property of cpu@0 and cpu@1. This patch fixes the spacing with the "clocks" property of cpu@0 and cpu@1. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a77965: add SSIU support for soundJiada Wang1-20/+231
rsnd driver supports SSIU now, let's use it. Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are no longer needed. Applies commit 8d14bfa074db ("arm64: dts: renesas: r8a7796: add SSIU support for sound") and commit 10bd03fa896e ("arm64: dts: renesas: r8a7796: remove BUSIF0 settings from rcar_sound,ssi") for r8a77965. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Timo Wischer <twischer@de.adit-jv.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: ebisu: Fix adv7482 hexadecimal register addressTakeshi Kihara1-1/+1
The register address used for the reg property of the adv7482 node in other Renesas device trees are decimal not hex, change this for Ebisu to align it with the others. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Niklas: rewrite commit message] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a77995: draak: Enable LVDS1 encoderLaurent Pinchart1-0/+7
The LVDS1 encoder must supply a pixel clock to the DU for the DPAD output when the LVDS0 encoder is used. Enable it despite its output not being connected. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18arm64: dts: renesas: r8a77990: ebisu: Enable LVDS1 encoderLaurent Pinchart1-0/+7
The LVDS1 encoder must supply a pixel clock to the DU for the DPAD output when the LVDS0 encoder is used. Enable it despite its output not being connected. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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