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2019-01-22arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU coreFabrizio Castro1-8/+17
Add a device node for the second Cortex-A53 CPU core on the Renesas RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks for the ARM Generic Interrupt Controller and Architectured Timer. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add watchdog supportFabrizio Castro1-0/+10
Add watchdog support to the RZ/G2E (a.k.a. R8A774C0) SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add Ethernet AVB nodeFabrizio Castro1-0/+45
This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add GPIO device nodesFabrizio Castro1-0/+105
Add GPIO device nodes to the DT of the r8a774c0 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add PFC supportFabrizio Castro1-0/+5
Add PFC support to the RZ/G2E (a.k.a. r8a774c0) SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add INTC-EX device nodeFabrizio Castro1-0/+16
Add support for the Interrupt Controller for External Devices (INTC-EX) on RZ/G2E. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodesFabrizio Castro1-0/+171
Add the device nodes for all RZ/G2E SCIF and HSCIF serial ports, including clocks, power domains and DMAs. According to the HW user manual, SCIF[015] and HSCIF[012] are connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and HSCIF[34] are connected to SYS-DMAC0. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a774c0: Add SYS-DMAC controller nodesFabrizio Castro1-0/+102
Add sys-dmac[012] device nodes for the RZ/G2E SoC (a.k.a. r8a774c0). Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: Initial device tree for r8a774c0Fabrizio Castro1-0/+186
Basic support for the RZ/G2E SoC (a.k.a. r8a774c0). Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-22arm64: dts: renesas: r8a77990: ebisu: Fix EthernetAVB phy mode to rgmiiKazuya Mizuguchi1-1/+0
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of August 24, 2018, the TX clock internal delay mode doesn't support on R-Car E3. This patch fixes EthernetAVB phy mode to rgmii. This is achieved by simply dropping the phy-mode property from r8a77990-ebisu.dts as the default property for this for r8a77990, as set in r8a77990.dtsi, is "rgmii". Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-01-22arm64: dts: imx8qxp: Fix MU4_INT numberDaniel Baluta1-1/+1
MU4_INT correct number is 180, while 179 is for MU3_INT. Fixes: 3d91ba65fecd ("arm64: dts: imx: add imx8qxp support") Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-21arm64: mm: make use of new memblocks_present() helperLogan Gunthorpe1-19/+1
Cleanup the arm64_memory_present() function seeing it's very similar to other arches. memblocks_present() is a direct replacement of arm64_memory_present() Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-01-21arm64: Remove asm/memblock.hWill Deacon4-23/+1
The arm64 asm/memblock.h header exists only to provide a function prototype for arm64_memblock_init(), which is called only from setup_arch(). Move the declaration into mmu.h, where it can live alongside other init functions such as paging_init() and bootmem_init() without the need for its own special header file. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-01-21arm64: asm-offsets: remove unused offsetsAndrew Murray1-20/+0
There are a number of offsets defined in asm-offsets.c which no longer have any users. Let's clean this up by removing them. All the remaining offsets are in use. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Andrew Murray <andrew.murray@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-01-21arm64: default NR_CPUS to 256Mark Rutland1-2/+1
There are shipping arm64 platforms with 256 hardware threads. So that we can make use of these with defconfig, bump the arm64 default NR_CPUS to 256. At the same time, drop a redundant comment. We only have one default for NR_CPUS, so there's nothing to sort. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-01-19arm64: perf: remove misleading commentAndrew Murray1-1/+1
The comment for the armv8pmu_set_event_filter function suggests that it only works for PMUv2 PMUs - this is incorrect. Let's remove the incorrect comment. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Andrew Murray <andrew.murray@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-01-17arm64: dts: meson-axg: add efuse deviceJerome Brunet1-0/+8
Add efuse to the AXG family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-17arm64: dts: meson: s400: fix emmc maximum rateJerome Brunet1-2/+1
Limiting the HS200 rate on the s400 was just a way to mask that the tuning setting were not correct. This seems to have been fixed with the recent MMC driver update. We can now use HS200 at full speed. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-17arm64: dts: meson: s400: enable sdr104 on sdioJerome Brunet1-1/+2
The bcm wifi/bt device on SDIO support SDR104 and it seems to work well following the recent mmc driver update, so enable this ultra high speed mode Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-17arm64: dts: meson-gx: add support for simplefbMaxime Jourdan3-0/+34
SimpleFB allows transferring a framebuffer from the firmware/bootloader to the kernel, while making sure the related clocks and power supplies stay enabled. Add nodes for CVBS and HDMI Simple Framebuffers. Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-17arm64: dts: meson-gx: Add canvas provider node to the vpuMaxime Jourdan1-0/+1
Allows the vpu driver to optionally use a canvas provider node. Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-17arm64: dts: rockchip: 'Fix' nanopi4 uSD card detectRobin Murphy1-7/+12
For whatever reason, the sdmmc_dectn function isn't working properly as-is, and microSD insertion and removal goes unnoticed. Using the pin as a GPIO interrupt instead is rather noisy without any debouncing, but is good enough to make it useful until someone feels inclined to figure out how the vendor kernel/firmware gets the dedicated function to work with no obvious difference in the pinmux/GRF configuration. Let's also take the opportunity to tweak the node name so that all related pins end up grouped together in the compiled DTB. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-01-17arm64: dts: rockchip: Add NanoPC-T4 IR receiverRobin Murphy1-0/+16
In common with most Rockchip reference designs, NanoPC-T4 has a passive IR receiver connected to PWM3. In lieu of a specialised driver for PWM-based IR pulse measurement, running the pin as a GPIO with the basic driver works perfectly well. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-01-17arm64: dts: rockchip: Refine nanopi4 differencesRobin Murphy3-54/+107
The nanopi4 boards differ primarily in their power trees, with the main 5V and 3.3V rails having very different topologies on the smaller USB-C powered boards vs. the 12V-powered T4, as well as minor variation in other regulators related to various external connectors. Additionally, the recovery key is only present on the T4 - ADC_IN1 is simply pulled high and not exposed on the other boards - and the lowest common denominator for MMC speed is actually HS200 according to the vendor DTs. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-01-17arm64: dts: rockchip: Add DT for NanoPi M4Robin Murphy2-0/+19
There are a number of subtle differences between the nanopi4 variants, and where they disagree, the common DTSI currently follows the details of NanoPi M4. In order to improve matters even more, let's add a separate DTS for the M4 to which we can start splitting things out appropriately. The third variant, NanoPi NEO4, is a lot closer to the M4 than either is to the larger T4, so arguably could get away with just sharing the M4 DT for now (plus I have neither of the smaller boards to actually test with). CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-01-17arm64: dts: renesas: r8a77965: Enable DMA for SCIF2Geert Uytterhoeven1-0/+3
SCIF2 on R-Car M3-N can be used with both DMAC1 and DMAC2. Fixes: 0ea5b2fd38db56aa ("arm64: dts: renesas: r8a77965: Add SCIF device nodes") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-17arm64: dts: renesas: r8a7796: Enable DMA for SCIF2Geert Uytterhoeven1-0/+3
SCIF2 on R-Car M3-W can be used with both DMAC1 and DMAC2. Fixes: dbcae5ea4bd27409 ("arm64: dts: r8a7796: Enable SCIF DMA") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-17arm64: dts: renesas: r8a774a1: Enable DMA for SCIF2Geert Uytterhoeven1-0/+3
SCIF2 on RZ/G2M can be used with both DMAC1 and DMAC2. Fixes: 3a3933a4fa36430a ("arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-16kasan, arm64: remove redundant ARCH_SLAB_MINALIGN defineAndrey Konovalov1-2/+0
Defining ARCH_SLAB_MINALIGN in arch/arm64/include/asm/cache.h when KASAN is off is not needed, as it is defined in defined in include/linux/slab.h as ifndef. Signed-off-by: Andrey Konovalov <andreyknvl@google.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-01-16arm64: kaslr: ensure randomized quantities are clean to the PoCArd Biesheuvel1-2/+6
kaslr_early_init() is called with the kernel mapped at its link time offset, and if it returns with a non-zero offset, the kernel is unmapped and remapped again at the randomized offset. During its execution, kaslr_early_init() also randomizes the base of the module region and of the linear mapping of DRAM, and sets two variables accordingly. However, since these variables are assigned with the caches on, they may get lost during the cache maintenance that occurs when unmapping and remapping the kernel, so ensure that these values are cleaned to the PoC. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Fixes: f80fb3a3d508 ("arm64: add support for kernel ASLR") Cc: <stable@vger.kernel.org> # v4.6+ Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-01-16arm64: kpti: Update arm64_kernel_use_ng_mappings() when forced onJames Morse1-1/+4
Since commit b89d82ef01b3 ("arm64: kpti: Avoid rewriting early page tables when KASLR is enabled"), a kernel built with CONFIG_RANDOMIZE_BASE can decide early whether to use non-global mappings by checking the kaslr_offset(). A kernel built without CONFIG_RANDOMIZE_BASE, instead checks the cpufeature static-key. This leaves a gap where CONFIG_RANDOMIZE_BASE was enabled, no kaslr seed was provided, but kpti was forced on using the cmdline option. When the decision is made late, kpti_install_ng_mappings() will re-write the page tables, but arm64_kernel_use_ng_mappings()'s value does not change as it only tests the cpufeature static-key if CONFIG_RANDOMIZE_BASE is disabled. This function influences PROT_DEFAULT via PTE_MAYBE_NG, and causes pgattr_change_is_safe() to catch nG->G transitions when the unchanged PROT_DEFAULT is used as part of PAGE_KERNEL_RO: [ 1.942255] alternatives: patching kernel code [ 1.998288] ------------[ cut here ]------------ [ 2.000693] kernel BUG at arch/arm64/mm/mmu.c:165! [ 2.019215] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP [ 2.020257] Modules linked in: [ 2.020807] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc2 #51 [ 2.021917] Hardware name: linux,dummy-virt (DT) [ 2.022790] pstate: 40000005 (nZcv daif -PAN -UAO) [ 2.023742] pc : __create_pgd_mapping+0x508/0x6d0 [ 2.024671] lr : __create_pgd_mapping+0x500/0x6d0 [ 2.058059] Process swapper/0 (pid: 1, stack limit = 0x(____ptrval____)) [ 2.059369] Call trace: [ 2.059845] __create_pgd_mapping+0x508/0x6d0 [ 2.060684] update_mapping_prot+0x48/0xd0 [ 2.061477] mark_linear_text_alias_ro+0xdc/0xe4 [ 2.070502] smp_cpus_done+0x90/0x98 [ 2.071216] smp_init+0x100/0x114 [ 2.071878] kernel_init_freeable+0xd4/0x220 [ 2.072750] kernel_init+0x10/0x100 [ 2.073455] ret_from_fork+0x10/0x18 [ 2.075414] ---[ end trace 3572f3a7782292de ]--- [ 2.076389] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b If arm64_kernel_unmapped_at_el0() is true, arm64_kernel_use_ng_mappings() should also be true. Signed-off-by: James Morse <james.morse@arm.com> CC: Ard Biesheuvel <ard.biesheuvel@linaro.org> CC: John Garry <john.garry@huawei.com> CC: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-01-16arm64: dts: imx8mq: add GPC power domainsLucas Stach1-0/+70
This adds support for the power domain controller found on the i.MX8MQ SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-16arm64: dts: imx8mq: Add pwm device nodesGuido Günther1-0/+44
We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-15arm64: dts: imx: add i.MX8QXP system controller RTC supportAnson Huang1-0/+4
Add i.MX8QXP system controller RTC support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-15arm64: dts: imx: add imx8qxp mek supportAisheng Dong2-0/+138
i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds imx8qxp mek board support. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-15arm64: dts: imx: add imx8qxp supportAisheng Dong1-0/+442
i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds the core SoC dtsi file support. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-15arm64: dts: allwinner: a64: Fix a typoJonathan Neuschäfer1-1/+1
This typo inverted the meaning of the comment, but the rest of the comment and the code reveal that the regulator in question needs to be on at all times. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-14arm64: dts: meson: Fix mmc cd-gpios polarityLoys Ollivier14-28/+14
Commit 89a5e15bcba8 ("gpio/mmc/of: Respect polarity in the device tree") changed the behavior of "cd-inverted" to follow the device tree bindings specification: According to SDHCI standard, CD lines are specified as "active low". Using the "cd-inverted" property means that the CD line is "active high". Fix the SD card description for meson by setting the cd-gpios as "active low", according to the boards specifications, and dropping the "cd-inverted" property. Fixes: 89a5e15bcba8 ("gpio/mmc/of: Respect polarity in the device tree") Signed-off-by: Loys Ollivier <lollivier@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-14arm64: dts: qcom: pm8916: Add PON watchdog nodeLoic Poulain1-0/+6
Add watchdog child node to the PM8916 PON device. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: Correct "gpiio" typo in msm8996-pinsJakob Wuhrer1-1/+1
gpiio5 is missspelt in msm8996-pins.dtsi, fix that. Signed-off-by: Jakob Wuhrer <jakobwuhrer@airmail.cc> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: apq8016-sbc: Increase load on l11 for SDCARDLoic Poulain1-0/+2
In the same way as for msm8974-hammerhead, l11 load, used for SDCARD VMMC, needs to be increased in order to prevent any voltage drop issues (due to limited current) happening with some SDCARDS or during specific operations (e.g. write). Tested on Dragonboard-410c and DART-SD410 boards. Fixes: 4c7d53d16d77 (arm64: dts: apq8016-sbc: add regulators support) Reported-by: Manabu Igusa <migusa@arrowjapan.com> Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: pms405: Export PMIC temperature to thermal frameworkAmit Kucheria1-0/+79
The PMS405 PMIC has an ADC that exposes the on-die temperature that we wire up to spmi-temp-alarm thermal driver. This allows the PMIC temperature to be exposed to Linux through the thermal framework. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: qcs404: Add WCN3990 WLAN module device nodeGovind Singh2-0/+24
Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on qcs404 soc. Optional clock and regulator controls are not yet available in upstream, hence add them once available. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: qcs404: sdcc1: enable HS400Jorge Ramirez-Ortiz1-0/+1
The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: sdm845: Add cpufreq device nodeTaniya Das1-0/+19
This change adds the cpufreq node as per the bindings example for SDM845. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add USB PHY lane twoEvan Green1-1/+3
Add the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtpCan Guo1-0/+14
Enable the UFS host controller and PHY on sdm845-mtp. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Can Guo <cang@codeaurora.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: add UFS controllerEvan Green1-0/+66
Add the UFS controller and PHY to SDM845. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> [bjorn: Add iommu context for the host controller] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: sdm845: Add node for arm,mmu-500Vivek Gautam1-0/+72
Add device node for arm,mmu-500 available on sdm845. This MMU-500 with single TCU and multiple TBU architecture is shared among all the peripherals except gpu. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtpEvan Green1-2/+56
Enable support for one of the micro SD slots on the MTP. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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