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2018-12-14arm64: dts: ti: k3-am654-base-board: Enable ECAP PWMVignesh R1-0/+11
Enable ECAP PWM which is used for LCD backlight. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am65-main: Add ECAP PWM nodeVignesh R1-0/+9
Add DT entry for ECAP0 PWM node present in main domain Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am654-base-board: Add I2C nodesVignesh R5-0/+142
Add DT entries for I2C instances present in AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: am654-base-board: Add pinmux for main uart0Vignesh R1-0/+16
Add pinmux for main uart0 that is serves as console on AM654 EVM Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-12-14arm64: dts: ti: k3-am65: Add pinctrl regionsTero Kristo3-0/+25
Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
2018-12-13arm64: dts: exynos: Add IMEM clock controller to Exynos5433Kamil Konieczny1-0/+15
Add node for IMEM clock controller, necessary for Security SubSystem (SSS) on Exynos5433. Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2018-12-13dma-mapping: bypass indirect calls for dma-directChristoph Hellwig1-3/+0
Avoid expensive indirect calls in the fast path DMA mapping operations by directly calling the dma_direct_* ops if we are using the directly mapped DMA operations. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Tony Luck <tony.luck@intel.com>
2018-12-13dma-direct: merge swiotlb_dma_ops into the dma_direct codeChristoph Hellwig1-1/+1
While the dma-direct code is (relatively) clean and simple we actually have to use the swiotlb ops for the mapping on many architectures due to devices with addressing limits. Instead of keeping two implementations around this commit allows the dma-direct implementation to call the swiotlb bounce buffering functions and thus share the guts of the mapping implementation. This also simplified the dma-mapping setup on a few architectures where we don't have to differenciate which implementation to use. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Tony Luck <tony.luck@intel.com>
2018-12-13dma-mapping: factor out dummy DMA opsRobin Murphy2-89/+1
The dummy DMA ops are currently used by arm64 for any device which has an invalid ACPI description and is thus barred from using DMA due to not knowing whether is is cache-coherent or not. Factor these out into general dma-mapping code so that they can be referenced from other common code paths. In the process, we can prune all the optional callbacks which just do the same thing as the default behaviour, and fill in .map_resource for completeness. Signed-off-by: Robin Murphy <robin.murphy@arm.com> [hch: moved to a separate source file] Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
2018-12-13dma-mapping: always build the direct mapping codeChristoph Hellwig1-1/+0
All architectures except for sparc64 use the dma-direct code in some form, and even for sparc64 we had the discussion of a direct mapping mode a while ago. In preparation for directly calling the direct mapping code don't bother having it optionally but always build the code in. This is a minor hardship for some powerpc and arm configs that don't pull it in yet (although they should in a relase ot two), and sparc64 which currently doesn't need it at all, but it will reduce the ifdef mess we'd otherwise need significantly. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Jesper Dangaard Brouer <brouer@redhat.com> Tested-by: Tony Luck <tony.luck@intel.com>
2018-12-13Merge branch 'yaml-bindings-for-v4.21' into dt/nextRob Herring6-26/+38
2018-12-13arm64: sysreg: Use _BITUL() when defining register bitsWill Deacon1-39/+40
Using shifts directly is error-prone and can cause inadvertent sign extensions or build problems with older versions of binutils. Consistent use of the _BITUL() macro makes these problems disappear. Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: cpufeature: Rework ptr auth hwcaps using multi_entry_cap_matchesWill Deacon3-89/+99
Open-coding the pointer-auth HWCAPs is a mess and can be avoided by reusing the multi-cap logic from the CPU errata framework. Move the multi_entry_cap_matches code to cpufeature.h and reuse it for the pointer auth HWCAPs. Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: cpufeature: Reduce number of pointer auth CPU caps from 6 to 4Will Deacon3-17/+8
We can easily avoid defining the two meta-capabilities for the address and generic keys, so remove them and instead just check both of the architected and impdef capabilities when determining the level of system support. Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: ptr auth: Move per-thread keys from thread_info to thread_structWill Deacon4-8/+7
We don't need to get at the per-thread keys from assembly at all, so they can live alongside the rest of the per-thread register state in thread_struct instead of thread_info. This will also allow straighforward whitelisting of the keys for hardened usercopy should we expose them via a ptrace request later on. Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: enable pointer authenticationMark Rutland1-0/+23
Now that all the necessary bits are in place for userspace, add the necessary Kconfig logic to allow this to be enabled. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: add prctl control for resetting ptrauth keysKristina Martsenko4-0/+55
Add an arm64-specific prctl to allow a thread to reinitialize its pointer authentication keys to random values. This can be useful when exec() is not used for starting new processes, to ensure that different processes still have different keys. Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: perf: strip PAC when unwinding userspaceMark Rutland2-1/+12
When the kernel is unwinding userspace callchains, we can't expect that the userspace consumer of these callchains has the data necessary to strip the PAC from the stored LR. This patch has the kernel strip the PAC from user stackframes when the in-kernel unwinder is used. This only affects the LR value, and not the FP. This only affects the in-kernel unwinder. When userspace performs unwinding, it is up to userspace to strip PACs as necessary (which can be determined from DWARF information). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: expose user PAC bit positions via ptraceMark Rutland5-2/+56
When pointer authentication is in use, data/instruction pointers have a number of PAC bits inserted into them. The number and position of these bits depends on the configured TCR_ELx.TxSZ and whether tagging is enabled. ARMv8.3 allows tagging to differ for instruction and data pointers. For userspace debuggers to unwind the stack and/or to follow pointer chains, they need to be able to remove the PAC bits before attempting to use a pointer. This patch adds a new structure with masks describing the location of the PAC bits in userspace instruction and data pointers (i.e. those addressable via TTBR0), which userspace can query via PTRACE_GETREGSET. By clearing these bits from pointers (and replacing them with the value of bit 55), userspace can acquire the PAC-less versions. This new regset is exposed when the kernel is built with (user) pointer authentication support, and the address authentication feature is enabled. Otherwise, the regset is hidden. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Cc: Will Deacon <will.deacon@arm.com> [will: Fix to use vabits_user instead of VA_BITS and rename macro] Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: add basic pointer authentication supportMark Rutland6-0/+104
This patch adds basic support for pointer authentication, allowing userspace to make use of APIAKey, APIBKey, APDAKey, APDBKey, and APGAKey. The kernel maintains key values for each process (shared by all threads within), which are initialised to random values at exec() time. The ID_AA64ISAR1_EL1.{APA,API,GPA,GPI} fields are exposed to userspace, to describe that pointer authentication instructions are available and that the kernel is managing the keys. Two new hwcaps are added for the same reason: PACA (for address authentication) and PACG (for generic authentication). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Tested-by: Adam Wallis <awallis@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> [will: Fix sizeof() usage and unroll address key initialisation] Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64/cpufeature: detect pointer authenticationMark Rutland3-1/+109
So that we can dynamically handle the presence of pointer authentication functionality, wire up probing code in cpufeature.c. From ARMv8.3 onwards, ID_AA64ISAR1 is no longer entirely RES0, and now has four fields describing the presence of pointer authentication functionality: * APA - address authentication present, using an architected algorithm * API - address authentication present, using an IMP DEF algorithm * GPA - generic authentication present, using an architected algorithm * GPI - generic authentication present, using an IMP DEF algorithm This patch checks for both address and generic authentication, separately. It is assumed that if all CPUs support an IMP DEF algorithm, the same algorithm is used across all CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: Don't trap host pointer auth use to EL2Mark Rutland1-1/+3
To allow EL0 (and/or EL1) to use pointer authentication functionality, we must ensure that pointer authentication instructions and accesses to pointer authentication keys are not trapped to EL2. This patch ensures that HCR_EL2 is configured appropriately when the kernel is booted at EL2. For non-VHE kernels we set HCR_EL2.{API,APK}, ensuring that EL1 can access keys and permit EL0 use of instructions. For VHE kernels host EL0 (TGE && E2H) is unaffected by these settings, and it doesn't matter how we configure HCR_EL2.{API,APK}, so we don't bother setting them. This does not enable support for KVM guests, since KVM manages HCR_EL2 itself when running VMs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Acked-by: Christoffer Dall <christoffer.dall@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: kvmarm@lists.cs.columbia.edu Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64/kvm: hide ptrauth from guestsMark Rutland2-0/+26
In subsequent patches we're going to expose ptrauth to the host kernel and userspace, but things are a bit trickier for guest kernels. For the time being, let's hide ptrauth from KVM guests. Regardless of how well-behaved the guest kernel is, guest userspace could attempt to use ptrauth instructions, triggering a trap to EL2, resulting in noise from kvm_handle_unknown_ec(). So let's write up a handler for the PAC trap, which silently injects an UNDEF into the guest, as if the feature were really missing. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: kvmarm@lists.cs.columbia.edu Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64/kvm: consistently handle host HCR_EL2 flagsMark Rutland3-4/+4
In KVM we define the configuration of HCR_EL2 for a VHE HOST in HCR_HOST_VHE_FLAGS, but we don't have a similar definition for the non-VHE host flags, and open-code HCR_RW. Further, in head.S we open-code the flags for VHE and non-VHE configurations. In future, we're going to want to configure more flags for the host, so lets add a HCR_HOST_NVHE_FLAGS defintion, and consistently use both HCR_HOST_VHE_FLAGS and HCR_HOST_NVHE_FLAGS in the kvm code and head.S. We now use mov_q to generate the HCR_EL2 value, as we use when configuring other registers in head.S. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: kvmarm@lists.cs.columbia.edu Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: add pointer authentication register bitsMark Rutland2-1/+32
The ARMv8.3 pointer authentication extension adds: * New fields in ID_AA64ISAR1 to report the presence of pointer authentication functionality. * New control bits in SCTLR_ELx to enable this functionality. * New system registers to hold the keys necessary for this functionality. * A new ESR_ELx.EC code used when the new instructions are affected by configurable traps This patch adds the relevant definitions to <asm/sysreg.h> and <asm/esr.h> for these, to be used by subsequent patches. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: add comments about EC exception levelsKristina Martsenko1-7/+7
To make it clear which exceptions can't be taken to EL1 or EL2, add comments next to the ESR_ELx_EC_* macro definitions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: perf: Treat EXCLUDE_EL* bit definitions as unsignedWill Deacon1-3/+3
Although the upper 32 bits of the PMEVTYPER<n>_EL0 registers are RES0, we should treat the EXCLUDE_EL* bit definitions as unsigned so that we avoid accidentally sign-extending the privilege filtering bit (bit 31) into the upper half of the register. Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 fieldWill Deacon1-0/+6
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked to see if a CPU is susceptible to Meltdown and therefore requires kpti to be enabled, existing CPUs do not implement this field. We therefore whitelist all unaffected Cortex-A CPUs that do not implement the CSV3 field. Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-13arm64: dts: renesas: draak: Fix CVBS inputLaurent Pinchart1-1/+1
A typo in the adv7180 DT node prevents successful probing of the VIN. Fix it. Fixes: 6a0942c20f5c ("arm64: dts: renesas: draak: Describe CVBS input") Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-13crypto: arm64/chacha - use combined SIMD/ALU routine for more speedArd Biesheuvel2-34/+238
To some degree, most known AArch64 micro-architectures appear to be able to issue ALU instructions in parellel to SIMD instructions without affecting the SIMD throughput. This means we can use the ALU to process a fifth ChaCha block while the SIMD is processing four blocks in parallel. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13crypto: arm64/chacha - optimize for arbitrary length inputsArd Biesheuvel2-37/+184
Update the 4-way NEON ChaCha routine so it can handle input of any length >64 bytes in its entirety, rather than having to call into the 1-way routine and/or memcpy()s via temp buffers to handle the tail of a ChaCha invocation that is not a multiple of 256 bytes. On inputs that are a multiple of 256 bytes (and thus in tcrypt benchmarks), performance drops by around 1% on Cortex-A57, while performance for inputs drawn randomly from the range [64, 1024) increases by around 30%. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13crypto: arm64/chacha - add XChaCha12 supportEric Biggers2-1/+19
Now that the ARM64 NEON implementation of ChaCha20 and XChaCha20 has been refactored to support varying the number of rounds, add support for XChaCha12. This is identical to XChaCha20 except for the number of rounds, which is 12 instead of 20. This can be used by Adiantum. Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13crypto: arm64/chacha20 - refactor to allow varying number of roundsEric Biggers3-49/+57
In preparation for adding XChaCha12 support, rename/refactor the ARM64 NEON implementation of ChaCha20 to support different numbers of rounds. Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13crypto: arm64/chacha20 - add XChaCha20 supportEric Biggers3-42/+124
Add an XChaCha20 implementation that is hooked up to the ARM64 NEON implementation of ChaCha20. This can be used by Adiantum. A NEON implementation of single-block HChaCha20 is also added so that XChaCha20 can use it rather than the generic implementation. This required refactoring the ChaCha20 permutation into its own function. Signed-off-by: Eric Biggers <ebiggers@google.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-13crypto: arm64/nhpoly1305 - add NEON-accelerated NHPoly1305Eric Biggers4-0/+188
Add an ARM64 NEON implementation of NHPoly1305, an ε-almost-∆-universal hash function used in the Adiantum encryption mode. For now, only the NH portion is actually NEON-accelerated; the Poly1305 part is less performance-critical so is just implemented in C. Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> # big-endian Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-12-12arm64: defconfig: Enable FSL_MC_BUS and FSL_MC_DPIOMarc Gonzalez1-0/+3
Commit e8342cc7954e ("enable CAAM crypto engine on QorIQ DPAA2 SoCs") enabled CRYPTO_DEV_FSL_DPAA2_CAAM, which depends on FSL_MC_DPIO, which is not set. Enable FSL_MC_BUS, and build FSL_MC_DPIO and CRYPTO_DEV_FSL_DPAA2_CAAM as modules. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> [olof: refreshed due to churn] Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12arm64: defconfig: Replace PINCTRL_MT7622 with PINCTRL_MTK_MOOREMarc Gonzalez1-0/+1
Commit e78d57b2f87c ("pinctrl: mediatek: add pinctrl-moore that implements the generic pinctrl dt-bindings") made PINCTRL_MT7622 depend on PINCTRL_MTK_MOORE, so it fell off in the refresh. Add MTK_MOORE, which automatically enables MT7622. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> [olof: refresh and minor commit message reword] Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12arm64: defconfig: Regenerate for v4.20Marc Gonzalez1-63/+49
Run the platform defconfig through kbuild, and handle the trivial case where options merely move around. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> [olof: refreshed due to some recent churn] Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'amlogic-dt64-2-redo' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dtOlof Johansson7-13/+24
arm64: dts: Amlogic updates for v4.21, round2 Highlights: - fix IRQ trigger type - AXG: enable GPIO IRQs, PHY IRQ, watchdog * tag 'amlogic-dt64-2-redo' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson: Fix IRQ trigger type for macirq arm64: dts: meson-axg: Enable GPIO interrupt controller arm64: dts: meson-axg: s400: Enable PHY interrupt arm64: dts: meson: add clock controller clock inputs dt-bindings: clk: meson: add main controller clock input dt-bindings: clk: meson: add ao controller clock inputs arm64: dts: meson-axg: remove alternate xtal arm64: dts: meson-axg: Enable watchdog on Meson AXG SoCs Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'v4.20-rockchip-dts64fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixesOlof Johansson1-8/+12
rockpro64 regulator fixes that cause stability issues * tag 'v4.20-rockchip-dts64fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: fix rk3399-rockpro64 regulator gpios Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dtOlof Johansson4-0/+244
Allwinner H3/H5 changes for 4.21 Our usual pull request with the changes shared between the H3 and H5 SoCs. The major changes for this release are: - Addition of the video engine for the H5 - H3 Camera support - New board: Emlid Neutis N5, Mapleboard MP130 * tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h5: Add Video Engine node ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes arm64: dts: allwinner: h5: Add system-control node with SRAM C1 ARM: dts: sun8i: h3: Fix the system-control register range ARM: dts: sun8i: Add the H3/H5 CSI controller ARM: dts: sun8i-h3: Add dts for the Mapleboard MP130 arm64: dts: allwinner: new board - Emlid Neutis N5 dt-bindings: vendor-prefix: new vendor - Emlid ARM: dts: sun8i-h3: add sy8106a to orange pi plus Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'renesas-soc-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/socOlof Johansson1-59/+1
Renesas ARM Based SoC Updates for v4.21 * pm-rmobile driver - Move to drivers/soc/renesas/ - Clean up struct rmobile_pm_domain * Renesas SoC Kconfig Symbols - Move symbols for ARM and SoCs to drivers/soc/renesas/ - Hide ARCH_RZN1 to improve consistency * SH-Mobile AG5 (sh73a0) SoC: Remove obsolete inclusion of <asm/smp_twd.h> * Restrict TWD and SCU to Renesas ARM based SoCs where they are present * Enable GPIOLIB on Renesas arm64 based SoCs to allow GPIO driver selection * tag 'renesas-soc-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/ ARM: shmobile: R-Mobile: Clean up struct rmobile_pm_domain ARM: shmobile: Move SoC Kconfig symbols to drivers/soc/renesas/ arm64: renesas: Move SoC Kconfig symbols to drivers/soc/renesas/ ARM: shmobile: Hide ARCH_RZN1 to improve consistency ARM: shmobile: sh73a0: Remove obsolete inclusion of <asm/smp_twd.h> ARM: shmobile: Restrict TWD support to SoCs that have it ARM: shmobile: Restrict SCU support to SoCs that have it arm64: renesas: Enable GPIOLIB to allow GPIO driver selection Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'sunxi-config64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/defconfigOlof Johansson1-0/+4
Allwinner arm64 defconfig for 4.21 A bunch of patches to improve the coverage of Allwinner drivers in the arm64 defconfig, mostly targeted at adding display drivers support. * tag 'sunxi-config64-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: defconfig: Enable PWM_SUN4I arm64: defconfig: Enable DRM_SUN8I_DW_HDMI arm64: defconfig: Enable DRM_SUN8I_MIXER arm64: defconfig: Enable MFD_AXP20X_I2C Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'v4.21-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dtOlof Johansson5-1/+184
Support for the onboard LEDs of the 2 96boards (ficus, rock960), hdmi output for rockpro64, vpu node on rk3399 and adding the always on 32kHz clock on rk3399-Gru to get a more complete clock tree. * tag 'v4.21-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add on-board LED support on rk3399-rock960 arm64: dts: rockchip: Add on-board LED support on rk3399-ficus arm64: dts: rockchip: enable hdmi output on rk3399-rockpro64 arm64: dts: rockchip: add VPU device node for RK3399 arm64: dts: rockchip: Add 32k clk on rk3399-gru Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'uniphier-dt-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dtOlof Johansson1-7/+4
UniPhier ARM SoC DT updates for v4.21 - Add bindings for all SoCs/boards of UniPhier platform - Move binding docs to socionext directory - Add all CPUs in cooling maps - Add MIO DMAC nodes * tag 'uniphier-dt-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: ARM: dts: uniphier: add MIO DMAC nodes arm64: dts: uniphier: Add all CPUs in cooling maps ARM: dts: uniphier: Add all CPUs in cooling maps dt-bindings: uniphier: move cache-uniphier.txt to vendor directory dt-bindings: uniphier: add bindings for UniPhier SoC family Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'imx-dt64-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dtOlof Johansson14-126/+1703
Freescale arm64 device tree update for 4.21: - Add device tree for LS1028A SoC and NXP FRWY & QDS boards support based on this SoC. - Add device tree for LX2160A SoC and NXP QDS & RDB boards support based on this SoC. - Add qdma devices for LS1043A and LS1046A SoC. - Disable PCIe device by default in SoC device tree and let board level device tree to enable as needed. - Drop compatible string "snps,dw-pcie" from LayerScape PCIe devices to avoid incorrect matching. - Move fsl-mc device as a child node of soc node, and add missing dma-ranges property for LS1088A SoC. - Update LayerScape SoCs' cooling maps to include all devices affected by individual trip points. * tag 'imx-dt64-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls1046a: add qdma device tree nodes arm64: dts: ls1043a: add qdma device tree nodes arm64: dts: ls1088a: Add missing dma-ranges property arm64: dts: ls1088a: Move fsl-mc node arm64: dts: fsl: Add all CPUs in cooling maps arm64: dts: Add support for NXP LS1028A SoC arm64: dts: layerscape: removed compatible string "snps,dw-pcie" arm64: dts: fsl: Add the status property disable PCIe arm64: dts: ls1012a: Add FRWY-LS1012A board support arm64: dts: add LX2160AQDS board support arm64: dts: add LX2160ARDB board support arm64: dts: add QorIQ LX2160A SoC support Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'v4.20-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dtOlof Johansson1-0/+10
mt8173: add node for the command queue device * tag 'v4.20-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: mt8173: Add GCE node Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'samsung-dt64-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dtOlof Johansson2-18/+42
Samsung DTS ARM64 changes for v4.21 1. Update DWC3 hardware modules to Exynos5433 specific variant. 2. Update cooling maps to include all CPU devices in multiple DTS files. * tag 'samsung-dt64-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Add all CPUs in cooling maps arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu into next/dtOlof Johansson7-330/+433
mvebu dt64 for 4.21 (part 1) - complete the description of the clearfog-gt-8k board (Armada 8040 based board) - declare eMMC on espressobin (Armada 3720 based board) which still need to be enable by the bootloader as it is not present on all the board. - add a new version of the Macchiatobin (Armada 8040 based board): the Single Shot (without the 10G 3310 PHYs). * tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu: arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB arm64: dts: add support for Macchiatobin Single Shot board arm64: dts: marvell: armada-37xx: Enable emmc on espressobin arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl definition arm64: dts: clearfog-gt-8k: enable mini-PCIe CON2 USB arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-12Merge tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dtOlof Johansson7-9/+725
Qualcomm ARM64 Updates for v4.21 Part 2 * Switch to use dwc3-qcom glue driver on MSM8996 * Fix issue with xo clk name on MSM8998 * Add cooling maps on MSM8916 * Add UART nodes on SDM845 * Add camera subsystem support on MSM8996 and MSM8916 * tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: msm8996: Use dwc3-qcom glue driver for USB arm64: dts: qcom: msm8998: Fixup clock to use xo_board arm64: dts: qcom: sdm845: Add UART nodes arm64: dts: qcom: msm8996: Add CAMSS support arm64: dts: qcom: msm8996: Add VFE SMMU node arm64: dts: qcom: Add pinctrls for camera sensors arm64: dts: qcom: Add Camera Control Interface pinctrls arm64: dts: qcom: msm8916: Add CAMSS support arm64: dts: qcom: msm8916: Add IOMMU sub-node for VFE context bank arm64: dts: msm8916: Add all CPUs in cooling maps Signed-off-by: Olof Johansson <olof@lixom.net>
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