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Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The RTC on Tegra186 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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In order for the correct interrupt type to be configured, the event
action for the power key needs to be "asserted".
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Enable these thermal zones to be able to monitor their temperatures and
control the fan to cool down the system if necessary.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The NVIDIA Tegra194 SoC defines six thermal zones. Define all of them in
device tree.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies
from the PMIC to the display block. Also enable the display hub which is
responsible for instantiating the display controllers. Finally, enable
the third SOR that drives the TMDS signals to the HDMI connector.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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We need the fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Pull ARM SoC fixes from Olof Johansson:
"Volume is a little higher than usual due to a set of gpio fixes for
Davinci platforms that's been around a while, still seemed appropriate
to not hold off until next merge window.
Besides that it's the usual mix of minor fixes, mostly corrections of
small stuff in device trees.
Major stability-related one is the removal of a regulator from DT on
Rock960, since DVFS caused undervoltage. I expect it'll be restored
once they figure out the underlying issue"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
MAINTAINERS: Remove unused Qualcomm SoC mailing list
ARM: davinci: dm644x: set the GPIO base to 0
ARM: davinci: da830: set the GPIO base to 0
ARM: davinci: dm355: set the GPIO base to 0
ARM: davinci: dm646x: set the GPIO base to 0
ARM: davinci: dm365: set the GPIO base to 0
ARM: davinci: da850: set the GPIO base to 0
gpio: davinci: restore a way to manually specify the GPIO base
ARM: davinci: dm644x: define gpio interrupts as separate resources
ARM: davinci: dm355: define gpio interrupts as separate resources
ARM: davinci: dm646x: define gpio interrupts as separate resources
ARM: davinci: dm365: define gpio interrupts as separate resources
ARM: davinci: da8xx: define gpio interrupts as separate resources
ARM: dts: at91: sama5d2: use the divided clock for SMC
ARM: dts: imx51-zii-rdu1: Remove EEPROM node
ARM: dts: rockchip: Remove @0 from the veyron memory node
arm64: dts: rockchip: Fix PCIe reset polarity for rk3399-puma-haikou.
arm64: dts: qcom: msm8998: Reserve gpio ranges on MTP
arm64: dts: sdm845-mtp: Reserve reserved gpios
arm64: dts: ti: k3-am654: Fix wakeup_uart reg address
...
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In commit 54a702f70589 ("kbuild: mark $(targets) as .SECONDARY and
remove .PRECIOUS markers"), I missed one important feature of the
.SECONDARY target:
.SECONDARY with no prerequisites causes all targets to be
treated as secondary.
... which agrees with the policy of Kbuild.
Let's move it to scripts/Kbuild.include, with no prerequisites.
Note:
If an intermediate file is generated by $(call if_changed,...), you
still need to add it to "targets" so its .*.cmd file is included.
The arm/arm64 crypto files are generated by $(call cmd,shipped),
so they do not need to be added to "targets", but need to be added
to "clean-files" so "make clean" can properly clean them away.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The arm64 codebase to implement coherent dma allocation for architectures
with non-coherent DMA is a good start for a generic implementation, given
that is uses the generic remap helpers, provides the atomic pool for
allocations that can't sleep and still is realtively simple and well
tested. Move it to kernel/dma and allow architectures to opt into it
using a config symbol. Architectures just need to provide a new
arch_dma_prep_coherent helper to writeback an invalidate the caches
for any memory that gets remapped for uncached access.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
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The dma remap code only makes sense for not cache coherent architectures
(or possibly the corner case of highmem CMA allocations) and currently
is only used by arm, arm64, csky and xtensa. Split it out into a
separate file with a separate Kconfig symbol, which gets the right
copyright notice given that this code was written by Laura Abbott
working for Code Aurora at that point.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Laura Abbott <labbott@redhat.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
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Pull arm64 fixes from Catalin Marinas:
- Cortex-A76 erratum workaround
- ftrace fix to enable syscall events on arm64
- Fix uninitialised pointer in iort_get_platform_device_domain()
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
ACPI/IORT: Fix iort_get_platform_device_domain() uninitialized pointer value
arm64: ftrace: Fix to enable syscall events on arm64
arm64: Add workaround for Cortex-A76 erratum 1286807
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ARM64: DT: Hisilicon SoCs DT updates for 4.21
* Hi3660 SoC and related boards:
- Standardize LED labels and triggers for the hikey960 board
- Add the missing cooling-cells property for the cpu nodes
- Add all cpus into the cooling maps
* Hi3670 SoC and related boards:
- Add clock nodes and update the uart clock
- Add Pinctrl, GPIO and uart nodes
- Enable uart and add GPIO line names for the hikey970 board
* Hi3798 SoC and related boards:
- Standardize LED labels and triggers for the poplar board
* Hi6220 SoC and related boards:
- Standardize LED labels and triggers for the hikey board
- Add all cpus into the cooling maps
* tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi:
ARM64: dts: hisilicon: Add all CPUs in cooling maps
arm64: dts: hi3660: Add missing cooling device properties for CPUs
arm64: dts: hisilicon: poplar: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey960: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey970: Add GPIO line names
arm64: dts: hisilicon: hikey970: Enable on-board UARTs
arm64: dts: hisilicon: hi3670: Add UART nodes
arm64: dts: hisilicon: hi3670: Add GPIO controller support
arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board
arm64: dts: hisilicon: Source SoC clock for UART6
arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
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arm64: Amlogic DT updates for v4.21
Some highlights:
- new boards: Phicomm N1 (S905D), Libretech S805-AC
- fixes for pinmux pad bias, GPIO line names
- AXG: enable SCPI, add secure monitor
* tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits)
arm64: dts: meson-gx: Add Internal Clock Measurer node
arm64: dts: amlogic: Add all CPUs in cooling maps
arm64: dts: meson: add libretech aml-s805x-ac board
dt-bindings: arm: amlogic: add libretech aml-s805x-ac bindings
dt-bindings: arm: amlogic: Add Phicomm N1
dt-bindings: Add vendor prefix for PHICOMM Co., Ltd.
arm64: dts: meson-gxl: add support for phicomm n1
arm64: dts: meson: consistently disable pin bias
arm64: dts: meson: disable pad bias for mmc pinmuxes
arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
arm64: dts: meson: s400: add bcm bluetooth device
arm64: dts: meson: p230: disable advertisement EEE for GbE.
arm64: dts: meson-axg: enable SCPI
Documentation: bindings: Add missing Amlogic SCPI sensor bindings
arm64: dts: meson-axg: correct sram shared mem unit-address
arm64: dts: meson-axg: fix mailbox address
arm64: dts: meson-gx: Add hdmi_5v regulator as hdmi tx supply
arm64: dts: meson-axg: add secure monitor
arm64: dts: meson-axg: s400: add cts-rts to the bluetooth uart
arm64: dts: meson-gxl-khadas-vim: fix GPIO lines names
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Modernize the Vexpress PL111 integration
Signed-off-by: Olof Johansson <olof@lixom.net>
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SoCFPGA DTS updates for v5.0
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
* tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
ARM: dts: socfpga: use tabs for indentation
arm: dts: socfpga: remove dma-mask property
arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Signed-off-by: Olof Johansson <olof@lixom.net>
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Renesas ARM64 Based SoC DT Updates for v4.21
* H3 (r8a7795) SoC:
- Remove unneeded sound #address/size-cells
* M3-W (r8a7796) SoC:
- Describe CMT (Compare Match Timer) devices in DT
- Describe I2C-DVFS device node in DT
* M3-N (r8a77965) SoC:
- Describe CAN, CANFD and LVDS in DT
* R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs:
- Describe CPU topology, capacity and cooling maps in DT
- Add SSIU support to R-Car audio
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs:
- Extend register range of HSUSB device to match documentation
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) based
Salvator-X, Salvator-XS and ULCB boards:
- Switch eMMC bus to 1V8
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) based
Salvator-X and Salvator-XS boards:
- Describe USB3.0 xHCI host and prerepheral devices as companions
* R-Car E3 (r8a77990) SoC:
- Add thermal support
- Add support for interupt controller for external devices (INTC-EX)
- Describe all SCIF devices and SYS-DMA for I2C and MSIOF devices
* R-Car E3 (r8a77990) based Ebisu board:
- Enable SDHI, CAN, CANFD, audio and USB3.0
- Describe serial console pins
* R-Car E3 (r8a77990) based Ebisu and
R-Car D3 (r8a77995) based Draak board:
- Enable USB2.0 peripheral device
* R-Car M3-N (r8a77965), E3 (r8a77990) and V3H (r8a77980) SoCs:
- Connect EtherAVB to IPMMU
* R-Car V3M (r8a77970) and V3H (r8a77980) SoCs:
- Describe TMU (timer unit), PWM timer controller and MSIOF devides in DT
- Add thermal support
* RZ/G2M (r8a774a1) SoC:
- Use clock and power index macros
- Describe VIN, CSI-2 and CAN devices in DT
* tag 'renesas-arm64-dt-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (40 commits)
arm64: dts: renesas: Add all CPUs in cooling maps
arm64: dts: renesas: r8a77990: add thermal device support
arm64: dts: renesas: r8a77990: Enable I2C DMA
arm64: dts: renesas: r8a7796: Add CMT device nodes
arm64: dts: renesas: r8a7796: add SSIU support for sound
arm64: dts: renesas: r8a77990: Add I2C-DVFS device node
arm64: dts: renesas: r8a77990: ebisu: Add and enable CAN,FD device nodes
arm64: dts: renesas: r8a77965: Add CAN and CANFD controller nodes
arm64: dts: renesas: r8a77990: ebisu: Add and enable PCIe device node
arm64: dts: renesas: Add CPU capacity-dmips-mhz
arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
arm64: dts: renesas: r8a774a1: Replace clock magic numbers
arm64: dts: renesas: r8a774a1: Replace power magic numbers
arm64: dts: renesas: r8a7795: add SSIU support for sound
arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering
arm64: dts: renesas: ebisu: Add and enable SDHI device nodes
arm64: dts: renesas: ebisu: Add serial console pins
arm64: dts: renesas: Switch eMMC bus to 1V8 on Salvator-X and ULCB
arm64: dts: renesas: r8a77990: Add all HSCIF nodes
arm64: dts: renesas: r8a779{7|8}0: add TMU support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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New dts for Gru-Scarlet (tablet device), default backlight brightness
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.
* tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add all CPUs in cooling maps
arm64: dts: rockchip: add Gru Scarlet devicetrees
arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator
arm64: dts: rockchip: Use default brightness table for rk3399-gru
arm64: dts: rockchip: add chosen node on rk3399-sapphire
arm64: dts: rockchip: enable HS200 for eMMC on rock64
arm64: dts: rockchip: add fan on rk3399-sapphire board
arm64: dts: rockchip: add rk3399 SPI DMAs
Signed-off-by: Olof Johansson <olof@lixom.net>
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Enable the GCC and PINCTRL for MSM8998 to make upstream boot to console.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Removal of vdd_log regulator on rk960 to fix a stability issue
and fixup of the pcie reset polarity on puma-haikou.
* tag 'v4.20-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Fix PCIe reset polarity for rk3399-puma-haikou.
arm64: dts: rockchip: remove vdd_log from rock960 to fix a stability issues
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
Signed-off-by: Ding Tao <miyatsu@qq.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Deassert the reset and wireless disable signals on the CON2 mini-PCIe
socket. That allows the host to detect USB devices on the mini-PCIe
socket.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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This reset signal controls the Marvell 1512 1G PHY.
Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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The fixed regulator driver ignores the gpio flags, so this change has
no practical effect in the current implementation. Fix it anyway to
correct the hardware description.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Pull tracing fixes from Steven Rostedt:
"While rewriting the function graph tracer, I discovered a design flaw
that was introduced by a patch that tried to fix one bug, but by doing
so created another bug.
As both bugs corrupt the output (but they do not crash the kernel), I
decided to fix the design such that it could have both bugs fixed. The
original fix, fixed time reporting of the function graph tracer when
doing a max_depth of one. This was code that can test how much the
kernel interferes with userspace. But in doing so, it could corrupt
the time keeping of the function profiler.
The issue is that the curr_ret_stack variable was being used for two
different meanings. One was to keep track of the stack pointer on the
ret_stack (shadow stack used by the function graph tracer), and the
other use case was the graph call depth. Although, the two may be
closely related, where they got updated was the issue that lead to the
two different bugs that required the two use cases to be updated
differently.
The big issue with this fix is that it requires changing each
architecture. The good news is, I was able to remove a lot of code
that was duplicated within the architectures and place it into a
single location. Then I could make the fix in one place.
I pushed this code into linux-next to let it settle over a week, and
before doing so, I cross compiled all the affected architectures to
make sure that they built fine.
In the mean time, I also pulled in a patch that fixes the sched_switch
previous tasks state output, that was not actually correct"
* tag 'trace-v4.20-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
sched, trace: Fix prev_state output in sched_switch tracepoint
function_graph: Have profiler use curr_ret_stack and not depth
function_graph: Reverse the order of pushing the ret_stack and the callback
function_graph: Move return callback before update of curr_ret_stack
function_graph: Use new curr_ret_depth to manage depth instead of curr_ret_stack
function_graph: Make ftrace_push_return_trace() static
sparc/function_graph: Simplify with function_graph_enter()
sh/function_graph: Simplify with function_graph_enter()
s390/function_graph: Simplify with function_graph_enter()
riscv/function_graph: Simplify with function_graph_enter()
powerpc/function_graph: Simplify with function_graph_enter()
parisc: function_graph: Simplify with function_graph_enter()
nds32: function_graph: Simplify with function_graph_enter()
MIPS: function_graph: Simplify with function_graph_enter()
microblaze: function_graph: Simplify with function_graph_enter()
arm64: function_graph: Simplify with function_graph_enter()
ARM: function_graph: Simplify with function_graph_enter()
x86/function_graph: Simplify with function_graph_enter()
function_graph: Create function_graph_enter() to consolidate architecture code
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The scm binding and driver was updated to rely on the fallback to the
default qcom,scm for any modern SoC and as such both are required. Add
the default compatible to make the scm instance probe.
Fixes: d850156a226a ("arm64: dts: qcom: msm8998: Add firmware node")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Improve the performance of the crc32() asm routines by getting rid of
most of the branches and small sized loads on the common path.
Instead, use a branchless code path involving overlapping 16 byte
loads to process the first (length % 32) bytes, and process the
remainder using a loop that processes 32 bytes at a time.
Tested using the following test program:
#include <stdlib.h>
extern void crc32_le(unsigned short, char const*, int);
int main(void)
{
static const char buf[4096];
srand(20181126);
for (int i = 0; i < 100 * 1000 * 1000; i++)
crc32_le(0, buf, rand() % 1024);
return 0;
}
On Cortex-A53 and Cortex-A57, the performance regresses but only very
slightly. On Cortex-A72 however, the performance improves from
$ time ./crc32
real 0m10.149s
user 0m10.149s
sys 0m0.000s
to
$ time ./crc32
real 0m7.915s
user 0m7.915s
sys 0m0.000s
Cc: Rui Sun <sunrui26@huawei.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The core ftrace hooks take the instrumented PC in x0, but for some
reason arm64's prepare_ftrace_return() takes this in x1.
For consistency, let's flip the argument order and always pass the
instrumented PC in x0.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Torsten Duwe <duwe@suse.de>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The save_return_regs and restore_return_regs macros are only used by
return_to_handler, and having them defined out-of-line only serves to
obscure the logic.
Before we complicate, let's clean this up and fold the logic directly
into return_to_handler, saving a few lines of macro boilerplate in the
process. At the same time, a missing trailing space is added to the
comments, fixing a code style violation.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Torsten Duwe <duwe@suse.de>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The core ftrace code requires that when it is handed the PC of an
instrumented function, this PC is the address of the instrumented
instruction. This is necessary so that the core ftrace code can identify
the specific instrumentation site. Since the instrumented function will
be a BL, the address of the instrumented function is LR - 4 at entry to
the ftrace code.
This fixup is applied in the mcount_get_pc and mcount_get_pc0 helpers,
which acquire the PC of the instrumented function.
The mcount_get_lr helper is used to acquire the LR of the instrumented
function, whose value does not require this adjustment, and cannot be
adjusted to anything meaningful. No adjustment of this value is made on
other architectures, including arm. However, arm64 adjusts this value by
4.
This patch brings arm64 in line with other architectures and removes the
adjustment of the LR value.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Torsten Duwe <duwe@suse.de>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The core frace code has an optional sanity check on the frame pointer
passed by ftrace_graph_caller and return_to_handler. This is cheap,
useful, and enabled unconditionally on x86, sparc, and riscv.
Let's do the same on arm64, so that we can catch any problems early.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Torsten Duwe <duwe@suse.de>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The global exports of ftrace_call and ftrace_graph_call are somewhat
painful to read. Let's use the generic GLOBAL() macro to ameliorate
matters.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Torsten Duwe <duwe@suse.de>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Commit 1212f7a16af4 ("scripts/kallsyms: filter arm64's __efistub_
symbols") updated the kallsyms code to filter out symbols with
the __efistub_ prefix explicitly, so we no longer require the
hack in our linker script to emit them as absolute symbols.
Cc: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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While commit 3b7e7848f0e88b36 ("arm64: dts: renesas: r8a7795: Add IPMMU
device nodes") for R-Car H3 ES2.0 did include power-domains properties,
they were forgotten in the counterpart for older R-Car H3 ES1.x SoCs.
Fixes: e4b9a493df45075b ("arm64: dts: renesas: r8a7795-es1: Add IPMMU device nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Aug 24, 2018)
removed the IPMMU-IR IOMMU instance on R-Car M3-N, as this SoC does not
have an Image Processing Unit (IMP-X5) nor the A3IR power domain.
Fixes: 55697cbb44e4f7ea ("arm64: dts: renesas: r8a779{65,80,90}: Add IPMMU devices nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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On arm64, all executable code is guaranteed to reside in the vmalloc
space (or the module space), and so jump targets will only use 48
bits at most, and the remaining bits are guaranteed to be 0x1.
This means we can generate an immediate jump address using a sequence
of one MOVN (move wide negated) and two MOVK instructions, where the
first one sets the lower 16 bits but also sets all top bits to 0x1.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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Pinebook has ACIN connector and 10000 mAh battery.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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AXP803 ACIN pins are routed from SOM to the DC jack on the baseboard.
AXP803 charger pins BATSENSE, LOADSENSE, N_BATDRV, LX_CHG, VIN_CHG
and IPSOUT are connected via PMOS driver to SOM VBAT pins. VBAT and
AXP803 TS pins are routed to the baseboard 3-pin battery connector.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Parts of the AXP803 are compatible with their counterparts on the AXP813.
Add DT nodes ADC, GPIO, AC and battery power supplies.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Enable a few core config options to be able to boot SDM845 MTP.
The GCC, PINCTRL and GENI options are required to be able to boot to a
console. Several clocks from GCC are parented by the "bi_tcxo" clock
from the RPMH clock driver, so enable this to save others the time to
debug the missing parent clocks later. RPMH depends on the COMMAND_DB.
While we're enabling the others let's do RPMH regulators as well, as
everything beyond this point depends on that.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The SDC2 control pins are typically used to manage sleep.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The externally accessible SD card slot on the MTP is driven by SDCC2.
Wire it up for use.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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SDCC2 is typically used as the controller for an external SD card slot.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The root parent clock of most msm8998 clock is the "xo" clock. The DT node
is incorrectly named "xo_board", which prevents Linux from correctly
parsing the clock tree, resulting in most clocks being unparented and
unable to be manipulated. The end result is that we can't turn on clocks
for peripherals like SD, so init usually fails.
Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
clock paths frequencies.
This patch adds the node in the top-level meson-gx dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Thierry Reding
Greg Kroah-Hartman
Linus Torvalds
Masahiro Yamada
Christoph Hellwig
Olof Johansson
Bjorn Andersson
Ding Tao
Baruch Siach
Ard Biesheuvel
Mark Rutland
Geert Uytterhoeven
Vasily Khoruzhick
Oskari Lemmela
Jeffrey Hugo
Andy Gross
Neil Armstrong