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2018-10-01arm64/numa: Report correct memblock range for the dummy nodeAnshuman Khandual1-1/+1
The dummy node ID is marked into all memory ranges on the system. So the dummy node really extends the entire memblock.memory. Hence report correct extent information for the dummy node using memblock range helper functions instead of the range [0LLU, PFN_PHYS(max_pfn) - 1)]. Fixes: 1a2db30034 ("arm64, numa: Add NUMA support for arm64 platforms") Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64/mm: Define esr_to_debug_fault_info()Anshuman Khandual1-1/+7
fault_info[] and debug_fault_info[] are static arrays defining memory abort exception handling functions looking into ESR fault status code encodings. As esr_to_fault_info() is already available providing fault_info[] array lookup, it really makes sense to have a corresponding debug_fault_info[] array lookup function as well. This just adds an equivalent helper function esr_to_debug_fault_info(). Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64/mm: Reorganize arguments for is_el1_permission_fault()Anshuman Khandual1-5/+4
Most memory abort exception handling related functions have the arguments in the order (addr, esr, regs) except is_el1_permission_fault(). This changes the argument order in this function as (addr, esr, regs) like others. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64/mm: Use ESR_ELx_FSC macro while decoding fault exceptionAnshuman Khandual1-1/+1
Just replace hard code value of 63 (0x111111) with an existing macro ESR_ELx_FSC when parsing for the status code during fault exception. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: arch_timer: Add workaround for ARM erratum 1188873Marc Zyngier4-1/+24
When running on Cortex-A76, a timer access from an AArch32 EL0 task may end up with a corrupted value or register. The workaround for this is to trap these accesses at EL1/EL2 and execute them there. This only affects versions r0p0, r1p0 and r2p0 of the CPU. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: compat: Add CNTFRQ trap handlerMarc Zyngier2-0/+16
Just like CNTVCT, we need to handle userspace trapping into the kernel if we're decided that the timer wasn't fit for purpose... 64bit userspace is already dealt with, but we're missing the equivalent compat handling. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: compat: Add CNTVCT trap handlerMarc Zyngier2-0/+19
Since people seem to make a point in breaking the userspace visible counter, we have no choice but to trap the access. We already do this for 64bit userspace, but this is lacking for compat. Let's provide the required handler. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: compat: Add cp15_32 and cp15_64 handler arraysMarc Zyngier1-0/+28
We're now ready to start handling CP15 access. Let's add (empty) arrays for both 32 and 64bit accessors, and the code that deals with them. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: compat: Add condition code checks and IT advanceMarc Zyngier1-0/+85
Here's a /really nice/ part of the architecture: a CP15 access is allowed to trap even if it fails its condition check, and SW must handle it. This includes decoding the IT state if this happens in am IT block. As a consequence, SW must also deal with advancing the IT state machine. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: compat: Add separate CP15 trapping hookMarc Zyngier2-2/+26
Instead of directly generating an UNDEF when trapping a CP15 access, let's add a new entry point to that effect (which only generates an UNDEF for now). Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: Add decoding macros for CP15_32 and CP15_64 trapsMarc Zyngier1-0/+52
So far, we don't have anything to help decoding ESR_ELx when dealing with ESR_ELx_EC_CP15_{32,64}. As we're about to handle some of those, let's add some useful macros. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01kvm: arm64: Add helper for loading the stage2 setting for a VMSuzuki K Poulose3-3/+12
We load the stage2 context of a guest for different operations, including running the guest and tlb maintenance on behalf of the guest. As of now only the vttbr is private to the guest, but this is about to change with IPA per VM. Add a helper to load the stage2 configuration for a VM, which could do the right thing with the future changes. Cc: Christoffer Dall <cdall@kernel.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01arm64: remove unused asm/compiler.h header fileArd Biesheuvel4-33/+0
arm64 does not define CONFIG_HAVE_ARCH_COMPILER_H, nor does it keep anything useful in its copy of asm/compiler.h, so let's remove it before anybody starts using it. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01arm64: compat: Provide definition for COMPAT_SIGMINSTKSZWill Deacon1-0/+1
arch/arm/ defines a SIGMINSTKSZ of 2k, so we should use the same value for compat tasks. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: Oleg Nesterov <oleg@redhat.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Reported-by: Steve McIntyre <steve.mcintyre@arm.com> Tested-by: Steve McIntyre <93sam@debian.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-09-30arm64: actions: Enable PINCTRL in platforms KconfigManivannan Sadhasivam1-0/+1
Select PINCTRL for Actions Semi SoCs. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s700: Set UART clock references from CMUSaravanan Sekar2-7/+7
Remove fixed clock in Cubieboard 7 and use Clock Management Unit clocks for all UART nodes in Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Moved/added to SoC] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s700: Add Clock Management UnitSaravanan Sekar1-0/+14
Add Clock Management Unit for Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add DMA ControllerManivannan Sadhasivam1-0/+13
Add DMA controller node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2Manivannan Sadhasivam1-0/+43
Add pinctrl definitions for Actions Semiconductor S900 I2C controllers. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Enable I2C1 and I2C2 exposed on the low speed expansion connector in Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Squashed] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add I2C controller nodesManivannan Sadhasivam1-0/+60
Add I2C controller nodes for Actions Semiconductor S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Squashed/added clocks, dropped pinctrl properties for now] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900-bubblegum-96: Add gpio line namesManivannan Sadhasivam1-0/+175
Add gpio line names to Actions Semi S900 based Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add gpio properties to pinctrl nodeManivannan Sadhasivam1-0/+3
Add gpio properties to pinctrl node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add pinctrl nodeManivannan Sadhasivam1-0/+6
Add pinctrl nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add SPS nodeManivannan Sadhasivam1-0/+6
Add Actions Semi S900 Smart Power System (SPS) node. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Source CMU clock for UARTsManivannan Sadhasivam2-7/+7
Remove fixed clock in Bubblegum-96 board and source CMU (Clock Management Unit) clock for UART nodes in Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [AF: Move/add clocks to SoC] Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30arm64: dts: actions: s900: Add Clock Management Unit nodesManivannan Sadhasivam1-0/+20
Add Actions Semi S900 Clock Management Unit (CMU) nodes. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-29ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device treesChen-Yu Tsai2-0/+12
Bananapi released an updated revision of the H3/H5 based Bananapi M2+. Version 1.2 enables voltage control for the CPU's regulator by using a GPIO line to toggle a MOSFET that can change the effective resistance value in the regulator's feedback network. This patch adds a common .dtsi file for this new revision, which includes the original common sunxi-bananapi-m2-plus.dtsi file, and adds the GPIO-controlled regulator and a cpu-supply reference. H3 and H5 variant dts files are added as well. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-29arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5Chen-Yu Tsai2-0/+12
The Bananapi M2 Plus H5 is a variant of the original Bananapi M2 Plus, with the H3 SoC replaced with an H5. Everything else is the same. Add a stub device tree incorporating the shared bananapi-m2-plus dtsi file. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-29arm64: dts: allwinner: h5: Add device node for Mali-450 GPUChen-Yu Tsai1-0/+43
The H5 has a Mali-450 GPU with 4 Pixel Processor cores. Interestingly, while the datasheet lists an interrupt line for the GPU's PMU, the hardware block itself doesn't seem to have it. Reads from the PMU address range all return zero, and writes are ignored. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-28arm64: dts: Add spi slave dtsLeilk Liu1-0/+11
This patch adds MT2712 spi slave into device tree. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-28arm64: use for_each_of_cpu_node iteratorRob Herring1-1/+1
Use the for_each_of_cpu_node iterator to iterate over cpu nodes. This has the side effect of defaulting to iterating using "cpu" node names in preference to the deprecated (for FDT) device_type == "cpu". Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arm-kernel@lists.infradead.org Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Rob Herring <robh@kernel.org>
2018-09-28Merge tag 'renesas-arm64-defconfig-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/defconfigArnd Bergmann1-0/+2
Renesas ARM64 Based SoC Defconfig Updates for v4.20 * Enable recently upstreamed RZ/G2E (r8a774c0) and RZ/G2M (r8a774a1) SoCs * tag 'renesas-arm64-defconfig-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: defconfig: enable R8A774C0 SoC arm64: defconfig: enable R8A774A1 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28Merge tag 'renesas-arm64-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dtArnd Bergmann12-60/+1052
Second Round of Renesas ARM64 Based SoC DT Updates for v4.20 * Remove unneeded status from thermal nodes * R-Car Gen 3 SoCs: - Use 400kHz for I2C DVFS bus - Revise USB2.0 properties * R-Car Gen 3 SoC based ULCB boards: Add default bootargs * R-Car M3-N (r8a77965) SoC based boards: Enable audio with DMA * R-Car V3M (r8a77970 and V3H (r8a77980) SoCs: - Add compare match timer (CMT) support - Add timer pulse unit (TPU) support * R-Car V3H (r8a77980) and E3 (r8a77990) SoCs: - Attach the SYS-DMAC to the IPMMU * E3 (r8a77990) SoC: Add display output support * R-Car E3 (r8a77990) based Ebisu board: - Enable HDMI and CVBS input, and VGA and HDMI display output * R-Car D3 (r8a77995) SoC: Add LVDS support * R-Car D3 (r8a77995) based Draak board: Enable HDMI display output * tag 'renesas-arm64-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: renesas: r8a77965: Add Sound and Audio DMAC device nodes arm64: dts: renesas: r8a77995: draak: Enable HDMI display output arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs arm64: dts: renesas: r8a77995: Add LVDS support arm64: dts: renesas: r8a77990: Add display output support arm64: dts: renesas: r8a779{7|8}0: add TPU support arm64: dts: renesas: revise properties for R-Car Gen3 SoCs' usb 2.0 arm64: dts: renesas: ulcb: add default bootargs arm64: dts: renesas: r8a779{7|8}0: add CMT support arm64: dts: renesas: gen3: use 400kHz for I2C DVFS bus arm64: dts: renesas: r8a77980: Attach the SYS-DMAC to the IPMMU arm64: dts: renesas: r8a77990: Attach the SYS-DMAC to the IPMMU arm64: dts: renesas: ebisu: Add HDMI and CVBS input arm64: dts: renesas: Remove unneeded status from thermal nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28Merge tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dtArnd Bergmann5-19/+143
arm64: tegra: Device tree changes for v4.20-rc1 This contains mostly device tree changes to support faster SDHCI modes on Tegra210 and Tegra186. * tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: I2C on Tegra194 is not compatible with Tegra114 arm64: dts: tegra186: Enable HS400 arm64: dts: tegra210: Enable HS400 arm64: dts: tegra186: Add SDMMC4 DQS trim value arm64: dts: tegra210: Add SDMMC4 DQS trim value arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 arm64: dts: tegra186: Add SDHCI tap and trim values arm64: dts: tegra210: Add SDHCI tap and trim values arm64: dts: tegra186: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add sdmmc pad auto calibration offsets arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V arm64: dts: Add Tegra186 sdmmc pinctrl voltage states arm64: dts: Add Tegra210 sdmmc pinctrl voltage states Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28arm64: defconfig: enable Rockchip Innosilicon hdmiphyHeiko Stuebner1-0/+1
The rk3228 and rk3328 socs use an MMIO-connected hdmi-phy from Innosilicon. So enable the necessary driver as module. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-28arm64: dts: rockchip: enable display nodes on rk3328-rock64Heiko Stuebner1-0/+16
Enable necessary nodes to get output on the hdmi port of the board. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-28arm64: dts: rockchip: add rk3328 display nodesHeiko Stuebner1-0/+53
Add the chain of display nodes from the core display-subsystem through the one vop to the dw-hdmi output. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Robin Murphy <robin.murphy@arm.com> changes in v3: - drop reg from hdmi-in-port changes in v2: - remove trailing 0 from vop irq
2018-09-28arm64: dts: rockchip: add Innosilicon hdmi phy node to rk3328Heiko Stuebner1-0/+14
The rk3328 uses a hdmiphy from Innosilicon, so add the necessary node to the rk3328 soc devicetree. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Robin Murphy <robin.murphy@arm.com>
2018-09-28Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dtArnd Bergmann5-2/+204
Amlogic ARM64 DT updates for v4.20, round 2 - new SoC support: basic support for G12A family - new board: Amlogic U200 board, using G12A SoC - fix SPI bus warnings from new dtc updates * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support dt-bindings: arm: amlogic: Add Meson G12A binding arm64: dts: meson: Fix erroneous SPI bus warnings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28Merge tag 'berlin64-dt-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin into next/dtArnd Bergmann1-0/+173
Berlin64 DT changes for v4.20 * tag 'berlin64-dt-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin: arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC dt-bindings: arm: syna: add support for the AS370 SoC dt-bindings: arm: move berlin binding documentation to syna.txt Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28arm64: dts: lg: Fix SPI controller node namesRob Herring2-4/+4
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the name enables dtc SPI bus checks. Cc: Chanho Min <chanho.min@lge.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28arm64: dts: amd: Fix SPI bus warningsRob Herring1-2/+2
dtc has new checks for SPI buses. Fix the warnings in node names. arch/arm64/boot/dts/amd/amd-overdrive.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi' arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi' arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi' Cc: Brijesh Singh <brijeshkumar.singh@amd.com> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28arm64: dts: marvell: armada-37xx: add nodes to support watchdogMarek Behún1-0/+13
This adds the system controller node for CPU Miscellaneous Registers (which is needed for the watchdog node) and the watchdog node. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-27signal/arm64: Use send_sig_fault where appropriateEric W. Biederman1-7/+3
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27signal/arm64: Add and use arm64_force_sig_ptrace_errno_trapEric W. Biederman3-1/+11
Add arm64_force_sig_ptrace_errno_trap for consistency with arm64_force_sig_fault and use it where appropriate. This adds the show_signal logic to the force_sig_errno_trap case, where it was apparently overlooked earlier. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27signal/arm64: In ptrace_hbptriggered name the signal description stringEric W. Biederman1-1/+2
This will let the description be reused shortly. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27signal/arm64: Remove arm64_force_sig_infoEric W. Biederman2-7/+0
The function has no more callers so remove it. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27signal/arm64: Add and use arm64_force_sig_mceerr as appropriateEric W. Biederman3-7/+10
Add arm64_force_sig_mceerr for consistency with arm64_force_sig_fault, and use it in the one location that can take advantage of it. This removes the fiddly filling out of siginfo before sending a signal reporting an memory error to userspace. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27signal/arm64: Add and use arm64_force_sig_fault where appropriateEric W. Biederman5-51/+25
Wrap force_sig_fault with a helper that calls arm64_show_signal and call arm64_force_sig_fault where appropraite. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2018-09-27signal/arm64: Only call set_thread_esr once in do_page_faultEric W. Biederman1-3/+1
This code is truly common between the signal sending cases so share it. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
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