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2022-02-25Merge tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dtArnd Bergmann7-18/+24
SoCFPGA dts updates for v5.18, part 1 - Cleanup of Altera/Intel ARMv7 and ARMv8 DTS and bindings * tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: (22 commits) ARM: dts: socfpga: cyclone5: align regulator node with dtschema ARM: dts: socfpga: arria10: align regulator node with dtschema arm64: dts: agilex: align pl330 node name with dtschema arm64: dts: stratix10: align pl330 node name with dtschema arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema arm64: dts: agilex: align mmc node names with dtschema arm64: dts: agilex: add board compatible for N5X DK arm64: dts: agilex: add board compatible for SoCFPGA DK arm64: dts: stratix10: align regulator node names with dtschema arm64: dts: stratix10: align mmc node names with dtschema arm64: dts: stratix10: move ARM timer out of SoC node arm64: dts: stratix10: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for Mercury AA1 ARM: dts: arria5: add board compatible for SoCFPGA DK dt-bindings: clock: intel,stratix10: convert to dtschema dt-bindings: intel: document Agilex based board compatibles dt-bindings: altera: document Stratix 10 based board compatibles dt-bindings: altera: document VT compatibles dt-bindings: altera: document Arria 10 based board compatibles ... Link: https://lore.kernel.org/r/20220211112556.98940-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'samsung-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann8-19/+1654
Samsung DTS ARM64 changes for v5.18 1. Minor improvements and dtschema fixes (node names, properties). 2. Fix issues pointed out by DT schema checks: - Add necessary clock controller inputs on Exynos7. - Add USB DWC3 supplies. - Drop old syscon phandle on Exynos5433. 3. Add initial Exynos850 support and WinLink E850-96 board using it. * tag 'samsung-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7 arm64: dts: exynos: drop unneeded syscon phandle in Exynos5433 LPASS arm64: dts: exynos: align pl330 node name with dtschema arm64: dts: exynos: Add initial E850-96 board support arm64: dts: exynos: Add initial Exynos850 SoC support arm64: dts: exynos: add USB DWC3 supplies to Espresso board arm64: dts: exynos: add necessary clock inputs in Exynos7 arm64: dts: exynos: Align MAX77843 nodes with dtschema on TM2 Link: https://lore.kernel.org/r/20220209145226.184375-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann7-0/+1116
Tesla FSD ARM64 changes for v5.18 Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry and defconfig change. This brings and enables this new platform. This includes clock controller bindings (header files with clock IDs) which are shared also with Tesla FSD SoC clock controller pull request. * tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: fsd: Add SPI device nodes arm64: defconfig: Enable Tesla FSD SoC arm64: dts: fsd: Add initial pinctrl support arm64: dts: fsd: Add initial device tree support dt-bindings: clock: Document FSD CMU bindings dt-bindings: clock: Add bindings definitions for FSD CMU blocks dt-bindings: arm: add Tesla FSD ARM SoC dt-bindings: add vendor prefix for Tesla Link: https://lore.kernel.org/r/20220204154112.133723-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25arm64: module: remove (NOLOAD) from linker scriptFangrui Song1-3/+3
On ELF, (NOLOAD) sets the section type to SHT_NOBITS[1]. It is conceptually inappropriate for .plt and .text.* sections which are always SHT_PROGBITS. In GNU ld, if PLT entries are needed, .plt will be SHT_PROGBITS anyway and (NOLOAD) will be essentially ignored. In ld.lld, since https://reviews.llvm.org/D118840 ("[ELF] Support (TYPE=<value>) to customize the output section type"), ld.lld will report a `section type mismatch` error. Just remove (NOLOAD) to fix the error. [1] https://lld.llvm.org/ELF/linker_script.html As of today, "The section should be marked as not loadable" on https://sourceware.org/binutils/docs/ld/Output-Section-Type.html is outdated for ELF. Tested-by: Nathan Chancellor <nathan@kernel.org> Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Fangrui Song <maskray@google.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20220218081209.354383-1-maskray@google.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: cpufeature: Remove cpu_has_fwb() checkVladimir Murzin1-9/+0
cpu_has_fwb() is supposed to warn user is following architectural requirement is not valid: LoUU, bits [29:27] - Level of Unification Uniprocessor for the cache hierarchy. Note When FEAT_S2FWB is implemented, the architecture requires that this field is zero so that no levels of data cache need to be cleaned in order to manage coherency with instruction fetches. LoUIS, bits [23:21] - Level of Unification Inner Shareable for the cache hierarchy. Note When FEAT_S2FWB is implemented, the architecture requires that this field is zero so that no levels of data cache need to be cleaned in order to manage coherency with instruction fetches. It is not really clear what user have to do if assertion fires. Having assertions about the CPU design like this inspire even more assertions to be added and the kernel definitely is not the right place for that, so let's remove cpu_has_fwb() altogether. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Link: https://lore.kernel.org/r/20220224164739.119168-1-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25Merge branch kvm-arm64/psci-1.1 into kvmarm-master/nextMarc Zyngier2-11/+56
* kvm-arm64/psci-1.1: : . : Limited PSCI-1.1 support from Will Deacon: : : This small series exposes the PSCI SYSTEM_RESET2 call to guests, which : allows the propagation of a "reset_type" and a "cookie" back to the VMM. : Although Linux guests only ever pass 0 for the type ("SYSTEM_WARM_RESET"), : the vendor-defined range can be used by a bootloader to provide additional : information about the reset, such as an error code. : . KVM: arm64: Remove unneeded semicolons KVM: arm64: Indicate SYSTEM_RESET2 in kvm_run::system_event flags field KVM: arm64: Expose PSCI SYSTEM_RESET2 call to the guest KVM: arm64: Bump guest PSCI version to 1.1 Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-25KVM: arm64: Remove unneeded semicolonsChangcheng Deng1-2/+2
Fix the following coccicheck review: ./arch/arm64/kvm/psci.c: 379: 3-4: Unneeded semicolon Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> [maz: squashed another instance of the same issue in the patch] Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20220223092750.1934130-1-deng.changcheng@zte.com.cn Link: https://lore.kernel.org/r/20220225122922.GA19390@willie-the-truck
2022-02-25arm64: tegra: Drop arm,armv8-pmuv3 compatible stringThierry Reding2-3/+3
The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific compatible strings instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25arm64: Add support of PAuth QARMA3 architected algorithmVladimir Murzin11-4/+97
QARMA3 is relaxed version of the QARMA5 algorithm which expected to reduce the latency of calculation while still delivering a suitable level of security. Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 APA3, bits [15:12] Indicates whether the QARMA3 algorithm is implemented in the PE for address authentication in AArch64 state. GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224124952.119612-4-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: cpufeature: Mark existing PAuth architected algorithm as QARMA5Vladimir Murzin2-10/+14
In preparation of supporting PAuth QARMA3 architected algorithm mark existing one as QARMA5, so we can distingwish between two. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224124952.119612-3-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: cpufeature: Account min_field_value when cheking secondaries for PAuthVladimir Murzin1-1/+1
In case, both boot_val and sec_val have value below min_field_value we would wrongly report that address authentication is supported. It is not a big issue because we enable address authentication based on boot cpu (and check there is correct). Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224124952.119612-2-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: dts: renesas: spider: Complete SCIF3 descriptionGeert Uytterhoeven1-0/+23
Complete the description of the serial console by adding RTS/CTS, the external clock crystal, and pin control. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/8e5701ca2a5f5925918217ab79e8489535339e7b.1645458249.git.geert+renesas@glider.be
2022-02-25arm64: dts: renesas: r8a779f0: Add pinctrl device nodeGeert Uytterhoeven1-0/+6
Add a device node for the Pin Function Controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that the register block does not include registers for banks 4-7, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
2022-02-25arm64: Change elfcore for_each_mte_vma() to use VMA iteratorLiam Howlett1-6/+17
Rework for_each_mte_vma() to use a VMA iterator instead of an explicit linked-list. This will allow easy integration with the maple tree work which removes the VMA list altogether. Signed-off-by: Liam R. Howlett <Liam.Howlett@oracle.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220218023650.672072-1-Liam.Howlett@oracle.com [will: Folded in fix from Catalin] Link: https://lore.kernel.org/r/YhUcywqIhmHvX6dG@arm.com Signed-off--by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: dts: marvell: armada-37xx: add device node for UART clock and use itPali Rohár1-2/+12
Define DT node for UART clock "marvell,armada-3700-uart-clock" and use this UART clock as a base clock for all UART devices. Reviewed-by: Marek Behún <kabel@kernel.org> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Link: https://lore.kernel.org/r/20220219152818.4319-7-kabel@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-25uaccess: remove CONFIG_SET_FSArnd Bergmann1-1/+1
There are no remaining callers of set_fs(), so CONFIG_SET_FS can be removed globally, along with the thread_info field and any references to it. This turns access_ok() into a cheaper check against TASK_SIZE_MAX. As CONFIG_SET_FS is now gone, drop all remaining references to set_fs()/get_fs(), mm_segment_t, user_addr_max() and uaccess_kernel(). Acked-by: Sam Ravnborg <sam@ravnborg.org> # for sparc32 changes Acked-by: "Eric W. Biederman" <ebiederm@xmission.com> Tested-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com> # for arc changes Acked-by: Stafford Horne <shorne@gmail.com> # [openrisc, asm-generic] Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25uaccess: generalize access_ok()Arnd Bergmann1-7/+4
There are many different ways that access_ok() is defined across architectures, but in the end, they all just compare against the user_addr_max() value or they accept anything. Provide one definition that works for most architectures, checking against TASK_SIZE_MAX for user processes or skipping the check inside of uaccess_kernel() sections. For architectures without CONFIG_SET_FS(), this should be the fastest check, as it comes down to a single comparison of a pointer against a compile-time constant, while the architecture specific versions tend to do something more complex for historic reasons or get something wrong. Type checking for __user annotations is handled inconsistently across architectures, but this is easily simplified as well by using an inline function that takes a 'const void __user *' argument. A handful of callers need an extra __user annotation for this. Some architectures had trick to use 33-bit or 65-bit arithmetic on the addresses to calculate the overflow, however this simpler version uses fewer registers, which means it can produce better object code in the end despite needing a second (statically predicted) branch. Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Mark Rutland <mark.rutland@arm.com> [arm64, asm-generic] Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Stafford Horne <shorne@gmail.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25arm64: simplify access_ok()Arnd Bergmann1-24/+10
arm64 has an inline asm implementation of access_ok() that is derived from the 32-bit arm version and optimized for the case that both the limit and the size are variable. With set_fs() gone, the limit is always constant, and the size usually is as well, so just using the default implementation reduces the check into a comparison against a constant that can be scheduled by the compiler. On a defconfig build, this saves over 28KB of .text. Acked-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25uaccess: add generic __{get,put}_kernel_nofaultArnd Bergmann1-2/+0
Nine architectures are still missing __{get,put}_kernel_nofault: alpha, ia64, microblaze, nds32, nios2, openrisc, sh, sparc32, xtensa. Add a generic version that lets everything use the normal copy_{from,to}_kernel_nofault() code based on these, removing the last use of get_fs()/set_fs() from architecture-independent code. Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-24Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-1/+1
tools/testing/selftests/net/mptcp/mptcp_join.sh 34aa6e3bccd8 ("selftests: mptcp: add ip mptcp wrappers") 857898eb4b28 ("selftests: mptcp: add missing join check") 6ef84b1517e0 ("selftests: mptcp: more robust signal race test") https://lore.kernel.org/all/20220221131842.468893-1-broonie@kernel.org/ drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c fb7e76ea3f3b6 ("net/mlx5e: TC, Skip redundant ct clear actions") c63741b426e11 ("net/mlx5e: Fix MPLSoUDP encap to use MPLS action information") 09bf97923224f ("net/mlx5e: TC, Move pedit_headers_action to parse_attr") 84ba8062e383 ("net/mlx5e: Test CT and SAMPLE on flow attr") efe6f961cd2e ("net/mlx5e: CT, Don't set flow flag CT for ct clear flow") 3b49a7edec1d ("net/mlx5e: TC, Reject rules with multiple CT actions") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-02-25arm64: dts: rockchip: add naneng combo phy nodes for rk3568Yifeng Zhao2-0/+68
Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220208091326.12495-5-yifeng.zhao@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-24Merge tag 'imx-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesArnd Bergmann3-2/+2
i.MX fixes for 5.17, round 2: - Drop reset signal from i.MX8MM vpumix power domain to fix a system hang. - Fix a dtbs_check warning caused by #thermal-sensor-cells in i.MX8ULP device tree. - Fix a clock disabling imbalance in gpcv2 driver. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-24Merge tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixesArnd Bergmann9-18/+42
Fix the display-port-sound on Gru devices, DDR voltage on the Quartz-A board, fix emmc signal-integrity and usb OTG mode on rk3399-puma as well as a number of dtschema fixes to make the reduce the number of errors. * tag 'v5.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: fix a typo on rk3288 crypto-controller ARM: dts: rockchip: reorder rk322x hmdi clocks arm64: dts: rockchip: reorder rk3399 hdmi clocks arm64: dts: rockchip: align pl330 node name with dtschema arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage arm64: dts: rockchip: Switch RK3399-Gru DP to SPDIF output arm64: dts: rockchip: fix rk3399-puma-haikou USB OTG mode arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568 arm64: dts: rockchip: fix dma-controller node names on rk356x Link: https://lore.kernel.org/r/1973741.CViHJPHrxy@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-24arm64: dts: qcom: sdm632: Add device tree for Fairphone 3Luca Weiss2-0/+184
Add device tree for the Fairphone 3 smartphone which is based on Snapdragon 632 (sdm632). Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-11-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: Add SDM632 device treeVladimir Lypak1-0/+81
Snapdragon 632 is based on msm8953 with some minor differences, mostly in the CPUs. SDM632 is using Kryo 250 instead of ARM Cortex A53 and has some differences in the thermal zones, mainly there being only one thermal zones for the first 4 cores (efficiency cores) but keeps one thermal zone per core for the remaining 4 cores (performance cores). Co-developed-by: Gabriel David <ultracoolguy@disroot.org> Signed-off-by: Gabriel David <ultracoolguy@disroot.org> Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-9-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: Add PM8953 PMICVladimir Lypak1-0/+90
Add a base DT for PM8953 PMIC, commonly used with MSM8953. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rayyan Ansari <rayyan@ansari.sh> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-8-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: Add MSM8953 device treeVladimir Lypak1-0/+1326
Add a base DT for MSM8953 SoC. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Co-developed-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220201909.445468-7-luca@z3ntu.xyz
2022-02-24arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensorNikita Travkin1-0/+23
L8150 uses LTR559 as a light and proximity sensor. Add it to the devicetree. Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220219145140.84712-1-nikita@trvn.ru
2022-02-24arm64: dts: qcom: align Google CROS EC PWM node name with dtschemaKrzysztof Kozlowski5-5/+5
dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220214081916.162014-4-krzysztof.kozlowski@canonical.com
2022-02-24arm64: tegra: Enable Jetson Xavier NX USB device modeWayne Chang1-0/+25
This commit enables USB device mode at J5 micro-B USB port of Jetson Xavier NX. Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable UART instance on 40-pin headerkartik1-0/+6
On P3737 board, UART-A is available on 40-pin header. Enable UART-A for P3737 and change the compatible string to "nvidia,tegra194-hsuart". This allows supporting HW flow control and is the preferred choice for higher baud rates. Signed-off-by: kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add HDA device tree node for Tegra234Mohan Kumar2-0/+21
Add HDA device tree node for Tegra234 chip and for Jetson AGX Orin platform. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable device-tree overlay supportJon Hunter1-0/+11
Add the '-@' DTC option for the Jetson TX1, Jetson Nano, Jetson TX2, Jetson TX2 NX, Jetson AGX Xavier, Jetson Xavier NX and Jetson AGX Orin platforms. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays on these platforms. These Jetson platforms have various expansion headers, including a 40-pin GPIO header, that allow various add-on modules to be connected and this permits users to create device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB from between 30-50%. For example, with v5.17-rc1 increase in size is as follows: tegra210-p2371-2180.dtb: 79580 -> 105744 bytes tegra210-p3450-0000.dtb: 57465 -> 81357 bytes tegra186-p2771-0000.dtb: 64763 -> 99553 bytes tegra186-p3509-0000+p3636-0001.dtb: 48078 -> 62464 bytes tegra194-p2972-0000.dtb: 75303 -> 111545 bytes tegra194-p3509-0000+p3668-0000.dtb: 74762 -> 111995 bytes tegra194-p3509-0000+p3668-0001.dtb: 74578 -> 111748 bytes tegra234-p3737-0000+p3701-0000.dtb: 11229 -> 12917 bytes Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: APE sound card for Jetson AGX OrinSameer Pujar2-0/+1797
Add audio-graph based sound card support on Jetson AGX Orin platform. The sound card binds following modules: * I/O interfaces such as I2S and DMIC (to be specific I2S1, I2S2, I2S4, I2S6 and DMIC3 instances). * HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all the available instances). Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add audio devices on Tegra234Sameer Pujar1-0/+419
Add following devices which are part of APE subsystem * ACONNECT, AGIC and ADMA * AHUB and children (ADMAIF, I2S, DMIC, DSPK, MVC, SFC, AMX, ADX and Mixer) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Move audio IOMMU properties to ADMAIF nodeThierry Reding1-5/+4
The ADMAIF node represents the device that accesses memory in the Tegra audio subsystem, so that's where the iommus and interconnects properties should reside. Move them out of the sound card node and into the ADMAIF node to properly reflect the memory data path. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add Tegra234 IOMMUsThierry Reding1-0/+426
The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by isochronous memory clients and two dual-instance ARM SMMUs used by non- isochronous memory clients. Add the corresponding device tree nodes and hook up existing memory clients (SDHCI and BPMP). Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Enable gpio-keys on Jetson AGX Orin Developer KitThierry Reding2-0/+32
Expose power, force-recovery and sleep buttons via a gpio-keys device so that userspace can receive events from them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add GPCDMA node for tegra186 and tegra194Akhil R2-0/+85
Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target. Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add Tegra234 PWM devicetree nodesAkhil R1-0/+12
Add device tree nodes for Tegra234 PWM Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add Tegra234 I2C devicetree nodesAkhil R1-0/+121
Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: Use the clearbhb instruction in mitigationsJames Morse10-0/+79
Future CPUs may implement a clearbhb instruction that is sufficient to mitigate SpectreBHB. CPUs that implement this instruction, but not CSV2.3 must be affected by Spectre-BHB. Add support to use this instruction as the BHB mitigation on CPUs that support it. The instruction is in the hint space, so it will be treated by a NOP as older CPUs. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-24KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migratedJames Morse3-1/+34
KVM allows the guest to discover whether the ARCH_WORKAROUND SMCCC are implemented, and to preserve that state during migration through its firmware register interface. Add the necessary boiler plate for SMCCC_ARCH_WORKAROUND_3. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-24arm64: Mitigate spectre style branch history side channelsJames Morse12-2/+352
Speculation attacks against some high-performance processors can make use of branch history to influence future speculation. When taking an exception from user-space, a sequence of branches or a firmware call overwrites or invalidates the branch history. The sequence of branches is added to the vectors, and should appear before the first indirect branch. For systems using KPTI the sequence is added to the kpti trampoline where it has a free register as the exit from the trampoline is via a 'ret'. For systems not using KPTI, the same register tricks are used to free up a register in the vectors. For the firmware call, arch-workaround-3 clobbers 4 registers, so there is no choice but to save them to the EL1 stack. This only happens for entry from EL0, so if we take an exception due to the stack access, it will not become re-entrant. For KVM, the existing branch-predictor-hardening vectors are used. When a spectre version of these vectors is in use, the firmware call is sufficient to mitigate against Spectre-BHB. For the non-spectre versions, the sequence of branches is added to the indirect vector. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
2022-02-24arm64: dts: renesas: Align GPIO hog names with dtschemaGeert Uytterhoeven7-9/+9
Dtschema expects GPIO hogs to end with a "hog" suffix. Also, the convention for node names is to use hyphens, not underscores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/baee4b9980576ffbab24122fce7147c9cbc2ea59.1645705998.git.geert+renesas@glider.be
2022-02-24arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdogBiju Das1-0/+14
Enable watchdog{0, 1, 2} interfaces on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220223165813.24833-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-23arm64: dts: qcom: Add support for Samsung Galaxy Book2Xilin Wu3-1/+750
Add support for Samsung Galaxy Book2 (W737) tablets. Currently working features: - Bootloader preconfigured display at 1280p - UFS - Wacom Digitizer - Two USB 3 ports - Sound - Bluetooth - Wi-Fi Signed-off-by: Xilin Wu <wuxilin123@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220223145130.544586-1-wuxilin123@gmail.com
2022-02-23arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1Dmitry Baryshkov1-5/+5
Convert all device tree xo_board users to the RPM_SMD_BB_CLK1 clock. Note, that xo_board can not be removed (yet), as clk-smd-rpm uses xo_board internally as the parent for all the clocks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-6-dmitry.baryshkov@linaro.org
2022-02-23arm64: dts: qcom: msm8996: add cxo and sleep-clk to gcc nodeDmitry Baryshkov1-2/+4
Supply proper cxo (RPM_SMD_BB_CLK1) and sleep_clk to the gcc clock controller node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-5-dmitry.baryshkov@linaro.org
2022-02-23arm64: dts: qcom: sdm845: add bi_tcxo to camccDmitry Baryshkov1-0/+2
Declare TCXO clock used for the Camera Clock Controller on SDM845. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220215201539.3970459-4-dmitry.baryshkov@linaro.org
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