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2020-06-24arm64: vdso: Don't use gcc plugins for building vgettimeofday.cAlexander Popov1-1/+1
Don't use gcc plugins for building arch/arm64/kernel/vdso/vgettimeofday.c to avoid unneeded instrumentation. Signed-off-by: Alexander Popov <alex.popov@linux.com> Link: https://lore.kernel.org/r/20200624123330.83226-4-alex.popov@linux.com Signed-off-by: Will Deacon <will@kernel.org>
2020-06-24arm64: vdso: Only pass --no-eh-frame-hdr when linker supports itWill Deacon1-2/+3
Commit 87676cfca141 ("arm64: vdso: Disable dwarf unwinding through the sigreturn trampoline") unconditionally passes the '--no-eh-frame-hdr' option to the linker when building the native vDSO in an attempt to prevent generation of the .eh_frame_hdr section, the presence of which has been implicated in segfaults originating from the libgcc unwinder. Unfortunately, not all versions of binutils support this option, which has been shown to cause build failures in linux-next: | CALL scripts/atomic/check-atomics.sh | CALL scripts/checksyscalls.sh | LD arch/arm64/kernel/vdso/vdso.so.dbg | ld: unrecognized option '--no-eh-frame-hdr' | ld: use the --help option for usage information | arch/arm64/kernel/vdso/Makefile:64: recipe for target | 'arch/arm64/kernel/vdso/vdso.so.dbg' failed | make[1]: *** [arch/arm64/kernel/vdso/vdso.so.dbg] Error 1 | arch/arm64/Makefile:175: recipe for target 'vdso_prepare' failed | make: *** [vdso_prepare] Error 2 Only link the vDSO with '--no-eh-frame-hdr' when the linker supports it. If we end up with the section due to linker defaults, the absence of CFI information in the sigreturn trampoline will prevent the unwinder from breaking. Link: https://lore.kernel.org/r/7a7e31a8-9a7b-2428-ad83-2264f20bdc2d@hisilicon.com Fixes: 87676cfca141 ("arm64: vdso: Disable dwarf unwinding through the sigreturn trampoline") Reported-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-06-23arm64: dts: qcom: angler: Add qcom,msm-id and pmic-idKonrad Dybcio1-0/+2
Add properties required for the bootloader to select the correct bootloader blob. They have been removed from the SoC device tree as they should be set on a per-device basis. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add PSCI nodeKonrad Dybcio1-0/+5
Add PSCI node to enable multi-processor startup. Note that not every 8994 device firmware supports PSCI, and even if, then it can only start the cores and not shut them down. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add pmu nodeKonrad Dybcio1-0/+5
Add the CPU PMU to get perf support for hardware events. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add I2C, SPI and BLSP DMA nodesKonrad Dybcio1-1/+155
Add support for I2C and SPI buses to enable peripherals such as touchscreens or sensors. Also add DMA nodes, configuration and BLSP2 UART2 interface. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add SDHCI1 nodeKonrad Dybcio1-0/+23
Enable support for SDHCI on msm8994-based devices. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add a proper CPU mapKonrad Dybcio1-10/+102
Add a proper CPU map to enable the use of all 8 cores. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add SPMI PMIC arbiter deviceKonrad Dybcio1-0/+16
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Modernize the DTS styleKonrad Dybcio2-95/+225
Following changes have been made: - remove name, compatible and msm-id - wrap clocks in clocks{} - order nodes by name and by address - clock_gcc -> gcc - msmgpio -> tlmm - qcom,smem -> smem - remove unit-address from smem - retire msm8994-pins.dtsi - add some of the missing pins - make comments C-style Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-2-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: defconfig: Enable Qualcomm IPCC driverBjorn Andersson1-0/+1
The IPCC hardware block provides a mechanism for triggering interrupts between co-processors in recent Qualcomm SoCs. This is used as basis for most form of communication between co-processors, so enable this support. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200622222747.717306-7-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: sm8250: Add remoteprocsBjorn Andersson2-0/+131
Add remoteproc nodes for the audio, compute and sensor cores, define glink for each one and enable them on the MTP with appropriate firmware defined. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200622222747.717306-6-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: sm8250: Add SMP2P nodesBjorn Andersson1-0/+72
SMP2P is used for interrupting and being interrupted about remoteproc state changes related to the audio, compute and sensor subsystems. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200622222747.717306-5-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: sm8250: Add QMP AOSS nodeBjorn Andersson1-0/+14
Add a node for the QMP AOSS. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200622222747.717306-4-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: sm8250: Add IPCCBjorn Andersson1-0/+10
Add the IPCC node, used to send and receive IPC signals with remoteprocs. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200622222747.717306-3-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: sm8250-mtp: Drop PM8150 ldo11Bjorn Andersson1-7/+0
PM8150 ldo11 on the MTP is wired to VDD_SSC_CX and controlled in levels, rather than as a regulator. As such it's available from the rpmhpd as the SM8250_LCX power domain. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Fixes: ec13d5c23a33 ("arm64: dts: qcom: sm8250-mtp: Add pm8150, pm8150l and pm8009") Link: https://lore.kernel.org/r/20200622222747.717306-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: defconfig: Enable Qualcomm SM8250 pinctrl driverBjorn Andersson1-0/+1
The SM8250 pinctrl driver provides pin configuration, pin muxing and GPIO pin control for many pins on the SM8250 SoC. Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200622220048.717073-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: tegra: Rename sdhci nodes to mmcThierry Reding15-36/+36
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add unit-address to memory nodeThierry Reding6-6/+6
The memory node requires a unit-address. For some boards the bootloader, which is usually locked down, uses a hard-coded name for the memory node without a unit-address, so we can't fix it on those boards. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Fixup I/O and PLL supply names for HDMI/DPThierry Reding4-8/+8
The I/O and PLL supplies used for HDMI/DP have alternative names. Use the names that are given in the hardware documentation for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove parent clock from display controllersThierry Reding2-12/+8
The display controller's parent clock depends on the output that's consuming data from the display controller, so it needs to be specified as the parent of the corresponding output. The device tree bindings do specify this, so just correct the existing device trees that get this wrong. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt-names for host1xThierry Reding4-0/+4
Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add Tegra132 compatible string for host1xThierry Reding1-1/+3
While the host1x controller found on Tegra132 is the same as on Tegra124 it is good practice to also list a SoC-specific compatible string so any SoC-specific quirks can be implemented in drivers if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt for Tegra194 memory controllerThierry Reding1-0/+1
This interrupt can be used for the operating system to be interrupted when certain events occur. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Describe interconnect paths on Tegra194Thierry Reding1-0/+70
On Tegra194, all clients of the memory subsystem can generally address 40 bits of system memory. However, bit 39 has special meaning and will cause the memory controller to reorder sectors for block-linear buffer formats. This is primarily useful for graphics-related devices. Use of bit 39 must be controlled on a case-by-case basis. Buffers that are used with bit 39 set by one device may be used with bit 39 cleared by other devices. Care must be taken to allocate buffers at addresses that do not require bit 39 to be set. This is normally not an issue for system memory since there are no Tegra-based systems with enough RAM to exhaust the 39-bit physical address space. However, when a device is behind an IOMMU, such as the ARM SMMU on Tegra194, the IOMMUs input address space can cause IOVA allocations to happen in this region. This is for example the case when an operating system implements a top-down allocation policy for IO virtual addresses. To account for this, describe the path that memory accesses take through the system. Memory clients will send requests to the memory controller, which forwards bits [38:0] of the address either to the external memory controller or the SMMU, depending on the stream ID of the access. A good way to describe this is using the interconnects bindings, see: Documentation/devicetree/bindings/interconnect/interconnect.txt The standard "dma-mem" path is used to describe the path towards system memory via the memory controller. A dma-ranges property in the memory controller's device tree node limits the range of DMA addresses that the memory clients can use to bits [38:0], ensuring that bit 39 is not used. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v4: - add additional entries for interconnect-names to match interconnects - add EMC as destination for interconnect paths Changes in v3: - add missing interconnect properties for VIC Changes in v2: - use memory client IDs instead of stream IDs (Mikko Perttunen) Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Describe interconnect paths on Tegra186Thierry Reding1-1/+55
The interface used by clients of the memory controller can be configured in a number of different ways. Describe this path using the interconnect bindings to enable the configuration of these parameters. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove extra compatible for Tegra210 SDHCIThierry Reding1-4/+4
The SDHCI on Tegra210 is in fact not compatible with the one found on Tegra124. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove extra compatible for Tegra194 SDHCIThierry Reding1-3/+3
The SDHCI on Tegra194 is in fact not compatible with the one found on Tegra186. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Use standard notation for interruptsThierry Reding1-2/+2
It is customary to use angle brackets around each tuple in the interrupts property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186Thierry Reding1-5/+5
The standard mmio-sram bindings require the #address- and #size-cells properties to be 1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add missing #phy-cells property on Jetson AGX XavierThierry Reding1-0/+1
PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add missing #phy-cells property on Jetson TX2Thierry Reding1-0/+2
PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: Depend on newer binutils when building PACMark Brown1-2/+2
Versions of binutils prior to 2.33.1 don't understand the ELF notes that are added by modern compilers to indicate the PAC and BTI options used to build the code. This causes them to emit large numbers of warnings in the form: aarch64-linux-gnu-nm: warning: .tmp_vmlinux.kallsyms2: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0000000 during the kernel build which is currently causing quite a bit of disruption for automated build testing using clang. In commit 15cd0e675f3f76b (arm64: Kconfig: ptrauth: Add binutils version check to fix mismatch) we added a dependency on binutils to avoid this issue when building with versions of GCC that emit the notes but did not do so for clang as it was believed that the existing check for .cfi_negate_ra_state was already requiring a new enough binutils. This does not appear to be the case for some versions of binutils (eg, the binutils in Debian 10) so instead refactor so we require a new enough GNU binutils in all cases other than when we are using an old GCC version that does not emit notes. Other, more exotic, combinations of tools are possible such as using clang, lld and gas together are possible and may have further problems but rather than adding further version checks it looks like the most robust thing will be to just test that we can build cleanly with the configured tools but that will require more review and discussion so do this for now to address the immediate problem disrupting build testing. Reported-by: KernelCI <bot@kernelci.org> Reported-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://github.com/ClangBuiltLinux/linux/issues/1054 Link: https://lore.kernel.org/r/20200619123550.48098-1-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2020-06-23arm64: compat: Remove 32-bit sigreturn code from the vDSOWill Deacon3-71/+0
The sigreturn code in the compat vDSO is unused. Remove it. Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-06-23arm64: compat: Always use sigpage for sigreturn trampolineWill Deacon1-25/+0
The 32-bit sigreturn trampoline in the compat sigpage matches the binary representation of the arch/arm/ sigpage exactly. This is important for debuggers (e.g. GDB) and unwinders (e.g. libunwind) since they rely on matching the instruction sequence in order to identify that they are unwinding through a signal. The same cannot be said for the sigreturn trampoline in the compat vDSO, which defeats the unwinder heuristics and instead attempts to use unwind directives for the unwinding. This is in contrast to arch/arm/, which never uses the vDSO for sigreturn. Ensure compatibility with arch/arm/ and existing unwinders by always using the sigpage for the sigreturn trampoline, regardless of the presence of the compat vDSO. Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-06-23arm64: compat: Allow 32-bit vdso and sigpage to co-existWill Deacon4-36/+32
In preparation for removing the signal trampoline from the compat vDSO, allow the sigpage and the compat vDSO to co-exist. For the moment the vDSO signal trampoline will still be used when built. Subsequent patches will move to the sigpage consistently. Acked-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-06-23arm64: vdso: Disable dwarf unwinding through the sigreturn trampolineWill Deacon2-21/+35
Commit 7e9f5e6629f6 ("arm64: vdso: Add --eh-frame-hdr to ldflags") results in a .eh_frame_hdr section for the vDSO, which in turn causes the libgcc unwinder to unwind out of signal handlers using the .eh_frame information populated by our .cfi directives. In conjunction with a4eb355a3fda ("arm64: vdso: Fix CFI directives in sigreturn trampoline"), this has been shown to cause segmentation faults originating from within the unwinder during thread cancellation: | Thread 14 "virtio-net-rx" received signal SIGSEGV, Segmentation fault. | 0x0000000000435e24 in uw_frame_state_for () | (gdb) bt | #0 0x0000000000435e24 in uw_frame_state_for () | #1 0x0000000000436e88 in _Unwind_ForcedUnwind_Phase2 () | #2 0x00000000004374d8 in _Unwind_ForcedUnwind () | #3 0x0000000000428400 in __pthread_unwind (buf=<optimized out>) at unwind.c:121 | #4 0x0000000000429808 in __do_cancel () at ./pthreadP.h:304 | #5 sigcancel_handler (sig=32, si=0xffff33c743f0, ctx=<optimized out>) at nptl-init.c:200 | #6 sigcancel_handler (sig=<optimized out>, si=0xffff33c743f0, ctx=<optimized out>) at nptl-init.c:165 | #7 <signal handler called> | #8 futex_wait_cancelable (private=0, expected=0, futex_word=0x3890b708) at ../sysdeps/unix/sysv/linux/futex-internal.h:88 After considerable bashing of heads, it appears that our CFI directives for unwinding out of the sigreturn trampoline are only processed by libgcc when both a .eh_frame_hdr section is present *and* the mysterious NOP is covered by an entry in .eh_frame. With both of these now in place, it has highlighted that our CFI directives are not comprehensive enough to restore the stack pointer of the interrupted context. This results in libgcc falling back to an arm64-specific unwinder after computing a bogus PC value from the unwind tables. The unwinder promptly dereferences this bogus address in an attempt to see if the pointed-to instruction sequence looks like the sigreturn trampoline. Restore the old unwind behaviour, which relied solely on heuristics in the unwinder, by removing the .eh_frame_hdr section from the vDSO and commenting out the insufficient CFI directives for now. Add comments to explain the current, miserable state of affairs. Cc: Tamas Zsoldos <tamas.zsoldos@arm.com> Cc: Szabolcs Nagy <szabolcs.nagy@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Daniel Kiss <daniel.kiss@arm.com> Acked-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2020-06-23arm64: dts: imx8mp: Add fallback compatible to ocotp nodeAnson Huang1-1/+1
Add "fsl,imx8mm-ocotp" as fallback compatible of i.MX8MP ocotp to support SoC serial_number read. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23arm64: dts: imx8qxp: Add ethernet aliasPeng Fan1-0/+2
Add ethernet alias, so bootloader code can use this to find the primary ethernet device, and set the MAC address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23arm64: dts: imx8qxp: add i2c aliasesPeng Fan1-0/+4
The devices could be enumerated properly with aliases. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23arm64: dts: imx8qxp: add alias for lsio MUPeng Fan1-0/+4
Add lsio mu alias for all lsio MUs that could communicate with SCU, imx_scu_enable_general_irq_channel will parse the alias to get the mu resource id, if using other MU, not MU1, the `mu_resource_id` is not what we expect, so add alias to fix this issue. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23KVM: arm64: vgic-v4: Plug race between non-residency and v4.1 doorbellMarc Zyngier1-0/+8
When making a vPE non-resident because it has hit a blocking WFI, the doorbell can fire at any time after the write to the RD. Crucially, it can fire right between the write to GICR_VPENDBASER and the write to the pending_last field in the its_vpe structure. This means that we would overwrite pending_last with stale data, and potentially not wakeup until some unrelated event (such as a timer interrupt) puts the vPE back on the CPU. GICv4 isn't affected by this as we actively mask the doorbell on entering the guest, while GICv4.1 automatically manages doorbell delivery without any hypervisor-driven masking. Use the vpe_lock to synchronize such update, which solves the problem altogether. Fixes: ae699ad348cdc ("irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer") Reported-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-23arm64: dts: qcom: Add support for Sony Xperia 10/10 Plus (Ganges platform)Martin Botka4-0/+75
Add device tree support for the Sony Xperia 10 and 10 Plus smartphones. They are all based on the Sony Ganges platform (sdm630/636) and share a lot of common code. The differences are really minor, so a Ganges-common DTSI has been created to reduce clutter. 10 - Kirin 10 Plus - Mermaid This platform is based on SoMC Nile, but there are some major differences when it comes to pin configuration and panel setup (among others). The boards currently support: * Screen console * SDHCI * I2C * pstore log dump * GPIO keys * PSCI idle states Signed-off-by: Martin Botka <martin.botka1@gmail.com> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Tested-by: Martin Botka <martin.botka1@gmail.com> Link: https://lore.kernel.org/r/20200622192558.152828-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: Add support for Sony Xperia XA2/Plus/Ultra (Nile platform)Konrad Dybcio5-0/+185
Add device tree support for the Sony Xperia XA2, XA2 Plus and XA2 Ultra smartphones. They are all based on the Sony Nile platform (sdm630) and share a lot of common code. The differences are really minor, so a Nile-common DTSI has been created to reduce clutter. XA2 - Pioneer XA2 Plus - Voyager XA2 Ultra - Discovery The boards currently support: * Screen console * SDHCI * I2C * pstore log dump * GPIO keys * PSCI idle states Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Tested-by: Ɓukasz Patron <priv.luk@gmail.com> Link: https://lore.kernel.org/r/20200622192558.152828-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: sdm630: Add sdm630 dts fileKonrad Dybcio1-0/+1174
Add devicetree files for SDM630 SoC and its pin configuration. This commit adds basic nodes like cpu, psci and other required configuration for booting up from eMMC to the serial console. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200622192558.152828-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: pm660(l): Add base dts filesKonrad Dybcio2-0/+86
Add base DTS files for pm660(l) along with GPIOs, power-on and rtc nodes. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200622192558.152828-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: imx8m: add mu nodePeng Fan4-0/+32
Add mu node to let A53 could communicate with M Core. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23arm64: dts: imx8m: change ocotp node name on i.MX8M SoCsAnson Huang4-4/+4
Change OCOTP node name from ocotp-ctrl to efuse to be compliant with yaml schema, it requires the nodename to be one of "eeprom|efuse|nvram". Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-22arm64: defconfig: Add CONFIG_QCOM_RPMPDJeffrey Hugo1-0/+1
RPMPD provides us the CS/MX power domains needed to boot the modem subsystem on msm8998 for wifi. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20200528184752.4747-1-jeffrey.l.hugo@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-22KVM: arm64: pvtime: Ensure task delay accounting is enabledAndrew Jones1-3/+12
Ensure we're actually accounting run_delay before we claim that we'll expose it to the guest. If we're not, then we just pretend like steal time isn't supported in order to avoid any confusion. Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200622142710.18677-1-drjones@redhat.com