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2020-03-12arm64: tegra: Add EEPROM suppliesJon Hunter5-0/+6
The following warning is observed on Jetson TX1, Jetson Nano and Jetson TX2 platforms because the supply regulators are not specified for the EEPROMs. WARNING KERN at24 0-0050: 0-0050 supply vcc not found, using dummy regulator WARNING KERN at24 0-0057: 0-0057 supply vcc not found, using dummy regulator For both of these platforms the EEPROM is powered by the main 1.8V supply rail and so populate the supply for these devices to fix these warnings. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Enable I2C controller for EEPROMJon Hunter1-0/+2
Commit a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1 module") populated the EEPROM on the Jetson TX1 module, but did not enable the corresponding I2C controller. Enable the I2C controller so that this EEPROM can be accessed. Fixes: a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1 module") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: smaug: Change clk_out_2 provider to PMCSowjanya Komatineni1-1/+1
clk_out_2 is a clock provided by the PMC, rather than the clock and reset controller, as previously erroneously defined. This patch changes clk_out_2 provider to PMC and uses corresponding PMC clock ID for clk_out_2. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add clock-cells property to Tegra PMC nodeSowjanya Komatineni2-3/+7
Tegra132 and Tegra210 PMC blocks have clk_out_1, clk_out_2, clk_out_3, and a blink clock as a part of the PMC. These clocks were erroneously provided by the clock and reset controller and are now provided by the PMC instead because that's where the primary controls are. Clock IDs for these clocks are defined in the PMC dt-bindings. This patch updates the device tree to include the PMC dt-bindings header and adds the #clock-cells property with one clock specifier to the PMC node. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Enable XUDC node on Jetson NanoNagarjuna Kristam1-1/+9
Enable XUSB device mode driver for USB 2-0 slot on Jetson Nano. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Update OTG port entries for Jetson NanoNagarjuna Kristam1-1/+11
Add usb-role-switch entry to peripheral USB port and add corresponding connector details. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Enable XUDC node on Jetson TX2Nagarjuna Kristam1-1/+8
Enable XUSB device mode driver for USB 2-0 slot on Jetson TX2. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add XUDC node for Tegra186Nagarjuna Kristam1-0/+19
Tegra186 has one XUSB device mode controller, which can be operated in HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Enable XUDC on Jetson TX1Nagarjuna Kristam1-1/+9
Enable XUSB device mode driver for USB 2-0 slot on Jetson TX1. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add XUDC node for Tegra210Nagarjuna Kristam1-0/+19
Tegra210 has one XUSB device mode controller, which can be operated in HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Update OTG port entries for Jetson TX2Nagarjuna Kristam1-1/+13
Add usb-role-switch entry to OTG USB port and add corresponding connector details. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Update OTG port entries for Jetson TX1Nagarjuna Kristam1-1/+23
Populate OTG vbus regulator and add usb-role-switch entry to USB 2-0 port and corresponding connector details. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Enable XUSB host in P2972-0000 boardJC Kuo2-1/+98
This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add XUSB and pad controller on Tegra194JC Kuo1-0/+139
Adds the XUSB pad and XUSB controllers on Tegra194. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Fix Tegra194 PCIe compatible stringJon Hunter1-6/+6
If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled then this can cause the kernel to incorrectly probe the generic designware PCIe platform driver instead of the Tegra194 designware PCIe driver. This causes a boot failure on Tegra194 because the necessary configuration to access the hardware is not performed. The order in which the compatible strings are populated in Device-Tree is not relevant in this case, because the kernel will attempt to probe the device as soon as a driver is loaded and if the generic designware PCIe driver is loaded first, then this driver will be probed first. Therefore, to fix this problem, remove the "snps,dw-pcie" string from the compatible string as we never want this driver to be probe on Tegra194. Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: dts: renesas: Add HiHope RZ/G2M board with idk-1110wr displayFabrizio Castro2-0/+53
The HiHope RZ/G2M is advertised as compatible with panel idk-1110wr from Advantech, however the panel isn't sold alongside the board. A new dts, adding everything that's required to get the panel to work with HiHope RZ/G2M, is the most convenient way to support the HiHope RZ/G2M when it's connected to the idk-1110wr. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1583957020-16359-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-12arm64: dts: renesas: r8a77990: Add CPUIdle support for CA53 coresTakeshi Kihara1-0/+15
Enable cpuidle (core shutdown) support for the CA53 cores on R-Car E3. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200309171200.21226-1-geert+renesas@glider.be
2020-03-12arm64: dts: renesas: r8a77965: Add CPUIdle support for CA57 coresTakeshi Kihara1-0/+15
Enable cpuidle (core shutdown) support for the CA57 cores on R-Car M3-N. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200309171112.21086-1-geert+renesas@glider.be
2020-03-12arm64: dts: renesas: r8a77961: salvator-xs: Fix memory unit-addressGeert Uytterhoeven1-1/+1
Correct the unit-address of the second memory node, to match the corresponding reg property. Fixes: 92980759c1699a3c ("arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200309170825.20882-1-geert+renesas@glider.be
2020-03-12arm64: dts: renesas: Add support for M3ULCB with R-Car M3-W+Yuya Hamamachi3-0/+34
Add initial support for the Renesas M3ULCB board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM. To avoid build error on 'ulcb.dtsi', ssi2 is added into 'r8a77961.dtsi'. Based on commit 92980759c1699a3c ("arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+"). Signed-off-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com> Link: https://lore.kernel.org/r/20200309064425.25437-3-yuya.hamamachi.sx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-12arm64: dts: renesas: r8a77961: Add thermal nodesGeert Uytterhoeven1-0/+79
Add a device node for the Thermal Sensor/Chip Internal Voltage Monitor in the R-Car M3-W+ (R8A77961) SoC, and describe the thermal zones. According to the R-Car Gen3 Hardware Manual Errata for Revision 2.00 of Jan 31, 2020, the thermal parameters for R-Car M3-W+ are the same as for R-Car M3-W. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200306110025.24747-1-geert+renesas@glider.be
2020-03-12arm64: dts: ls1028a: add missing LPUART nodesMichael Walle1-0/+73
The LS1028A has six LPUART controllers. Add the nodes. This was tested on a custom board. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200307091302.14881-2-michael@walle.cc Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-11arm64: dts: qcom: sc7180: Update reg names for SDHCVeerabhadrarao Badiganti1-2/+1
Remove the redundant _mem suffix for SDHC reg names. For SDcard instance, no need supply reg names since hc reg map is accessed with index. So remove reg names for SDcard. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1583946863-24308-2-git-send-email-vbadigan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-11arm64: dts: qcom: qcs404: Enable CQE support for eMMCVeerabhadrarao Badiganti2-1/+2
Enabling CQE support for eMMC by supplying the correct reg name and flag which indicates CQE support. Also remove the redundant _mem suffix for reg names. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1583946863-24308-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-11arm64: defconfig: Enable Truly NT35597 WQXGA panelBjorn Andersson1-0/+1
The Truly NT35597 WQXGA panel is found on the Qualcomm SDM845 MTP, enable the driver for it. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/20200311233039.928605-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-11arm64: dts: msm8916: Add fastrpc nodeSrinivas Kandagatla1-0/+14
Add fastrpc device node for adsp with one compute bank. Tested-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20200310175452.7503-1-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-12arm64: dts: allwinner: a64: add node for rotation coreJernej Skrabec1-0/+12
Allwinner A64 contains rotation core compatible to A83T. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-12arm64: dts: allwinner: a64: Fix display clock register rangeJernej Skrabec1-1/+1
Register range of display clocks is 0x10000, as it can be seen from DE2 documentation. Fix it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Fixes: 2c796fc8f5dbd ("arm64: dts: allwinner: a64: add necessary device tree nodes for DE2 CCU") [wens@csie.org: added fixes tag] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11arm64: entry: unmask IRQ in el0_sp()Mark Rutland1-1/+1
Currently, the EL0 SP alignment handler masks IRQs unnecessarily. It does so due to historic code sharing of the EL0 SP and PC alignment handlers, and branch predictor hardening applicable to the EL0 SP handler. We began masking IRQs in the EL0 SP alignment handler in commit: 5dfc6ed27710c42c ("arm64: entry: Apply BP hardening for high-priority synchronous exception") ... as this shared code with the EL0 PC alignment handler, and branch predictor hardening made it necessary to disable IRQs for early parts of the EL0 PC alignment handler. It was not necessary to mask IRQs during EL0 SP alignment exceptions, but it was not considered harmful to do so. This masking was carried forward into C code in commit: 582f95835a8fc812 ("arm64: entry: convert el0_sync to C") ... where the SP/PC cases were split into separate handlers, and the masking duplicated. Subsequently the EL0 PC alignment handler was refactored to perform branch predictor hardening before unmasking IRQs, in commit: bfe298745afc9548 ("arm64: entry-common: don't touch daif before bp-hardening") ... but the redundant masking of IRQs was not removed from the EL0 SP alignment handler. Let's do so now, and make it interruptible as with most other synchronous exception handlers. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: James Morse <james.morse@arm.com>
2020-03-11arm64: Mark call_smc_arch_workaround_1 as __maybe_unusedNathan Chancellor1-1/+1
When building allnoconfig: arch/arm64/kernel/cpu_errata.c:174:13: warning: unused function 'call_smc_arch_workaround_1' [-Wunused-function] static void call_smc_arch_workaround_1(void) ^ 1 warning generated. Follow arch/arm and mark this function as __maybe_unused. Fixes: 4db61fef16a1 ("arm64: kvm: Modernize __smccc_workaround_1_smc_start annotations") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-11arm64: entry-ftrace.S: Fix missing argument for CONFIG_FUNCTION_GRAPH_TRACER=yKunihiko Hayashi1-1/+1
Missing argument of another SYM_INNER_LABEL() breaks build for CONFIG_FUNCTION_GRAPH_TRACER=y. Fixes: e2d591d29d44 ("arm64: entry-ftrace.S: Convert to modern annotations for assembly functions") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Mark Brown <broonie@kernel.org>
2020-03-11arm64: dts: add bus to rockchip amba nodenamesJohan Jonker5-5/+5
A test with the command below gives for example this error: arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: amba: $nodename:0: 'amba' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' AMBA is a open standard for the connection and management of functional blocks in a SoC. It's compatible with 'simple-bus', so fix this error by adding 'bus' to all Rockchip 'amba' nodes. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ schemas/simple-bus.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200302153047.17101-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: imx8mq-phanbell: Fix Ethernet PHY post-reset durationAlifer Moraes1-1/+1
i.MX8MQ Phanbell board uses Realtek RTL8211FD as Ethernet PHY. Its datasheet states that the proper post reset duration should be at least 50 ms. Fixes: f34d4bfab354 ("arm64: dts: imx8mq-phanbell: Add support for ethernet") Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: enable fspi in imx8mm dtsAdam Ford1-1/+15
Pull in downstream patch from NXP repository to enable fspi device. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: imx8mn: align name for crypto child nodesSilvano di Ninno1-3/+3
crypto child nodes should use the "jr" name (without an index), as indicated in the DT binding. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: rockchip: replace clock-freq-min-max by max-frequencyJohan Jonker2-2/+2
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "synopsys-dw-mshc-common.yaml#" allOf: - $ref: "mmc-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine rockchip-dw-mshc.yaml, synopsys-dw-mshc-common.yaml and mmc-controller.yaml it gives for example this error: arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dt.yaml: mmc@fe320000: 'clock-freq-min-max' does not match any of the regexes: '^.*@[0-9]+$', '^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)| uhs-(sdr(12|25|50|104)|ddr50))$', 'pinctrl-[0-9]+' 'clock-freq-min-max' is deprecated, so replace it by 'max-frequency'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200307134841.13803-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: rockchip: fix vqmmc-supply property name for rk3399 pumaJohan Jonker1-1/+1
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "synopsys-dw-mshc-common.yaml#" allOf: - $ref: "mmc-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine rockchip-dw-mshc.yaml, synopsys-dw-mshc-common.yaml and mmc-controller.yaml it gives this error: arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dt.yaml: mmc@fe320000: 'vqmmc' does not match any of the regexes: '^.*@[0-9]+$', '^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)| uhs-(sdr(12|25|50|104)|ddr50))$', 'pinctrl-[0-9]+' 'vqmmc' is not a valid property name for mmc nodes. Fix this error by renaming it to 'vqmmc-supply'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200307134841.13803-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: remove no-emmc from mmc node for Rockchip PX5 EVBJohan Jonker1-1/+0
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "synopsys-dw-mshc-common.yaml#" allOf: - $ref: "mmc-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine rockchip-dw-mshc.yaml, synopsys-dw-mshc-common.yaml and mmc-controller.yaml it gives this error: arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dt.yaml: mmc@ff0c0000: 'no-emmc' does not match any of the regexes: '^.*@[0-9]+$', '^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)| uhs-(sdr(12|25|50|104)|ddr50))$', 'pinctrl-[0-9]+' 'no-emmc' is not a valid property name for mmc nodes, so remove it. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200307134841.13803-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: rockchip: remove rockchip,grf from vop nodes for px30Johan Jonker1-2/+0
An experimental test with the command below without additional properties in 'rockchip-vop.yaml' gives this error: arch/arm64/boot/dts/rockchip/px30-evb.dt.yaml: vop@ff470000: 'power-domains', 'rockchip,grf' do not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/rockchip/px30-evb.dt.yaml: vop@ff460000: 'power-domains', 'rockchip,grf' do not match any of the regexes: 'pinctrl-[0-9]+' 'rockchip,grf' is not used by the Rockchip VOP driver, so remove it from 'vop' nodes in 'px30.dtsi'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/ rockchip/rockchip-vop.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200309081600.3887-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: rockchip: remove max-freq from &spi1 node for Hugsun X99Johan Jonker1-1/+0
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "spi-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine spi-rockchip.yaml and spi-controller.yaml it gives this error: arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dt.yaml: spi@ff1d0000: 'max-freq' does not match any of the regexes: '^.*@[0-9a-f]+$', '^slave$' 'max-freq' is not a valid property name for spi nodes, so remove it. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/spi-rockchip.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200309125145.14455-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: lx2160aqds: Add FSPI node propertiesKuldeep Singh1-0/+15
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected on different buses, only one flash can be probed at a time. Add fspi node properties aligned with LX2160A-RDB fspi properties. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: lx2160ardb: Update FSPI node propertiesKuldeep Singh1-2/+2
Update fspi node compatibles of LX2160A-RDB to "jedec,spi-nor" for automatic detection of flash. This also helps in fixing below warning: spi-nor spi0.0: found mt35xu512aba, expected m25p80 spi-nor spi0.1: found mt35xu512aba, expected m25p80 Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: imx8mq-phanbell: Add gpio-fan/thermal supportVitor Massaru Iha2-1/+64
It was based on Google Source Code for Coral Edge TPU Mendel release: https://coral.googlesource.com/linux-imx/ It was tested on Coral Dev Board using this command: sudo stress --cpu 4 --timeout 3600 Signed-off-by: Vitor Massaru Iha <vitor@massaru.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: layerscape: add iommu-map property to pci nodesHou Zhiqiang3-0/+13
Add the iommu-map property to the pci nodes so that the firmware fixes it up with the required values thus enabling iommu for devices connected over pci. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: imx8mp-evk: Enable pca6416 on i2c3 busAnson Huang1-0/+7
Enable pca6416 on i.MX8MP EVK board's i2c3 bus. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: imx8mp-evk: Add i2c3 supportAnson Huang1-0/+14
Enable i2c3 for i.MX8MP EVK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: imx8mn-evk: Enable pca6416 on i2c3 busAnson Huang1-0/+7
Enable pca6416 on i.MX8MN EVK board's i2c3 bus. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: imx8mn-evk: Add i2c3 supportAnson Huang1-0/+14
Enable i2c3 for i.MX8MN EVK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: rockchip: fix compatible property for rk3399-evbJohan Jonker1-2/+1
A test with the command below gives this error: arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: /: compatible: ['rockchip,rk3399-evb', 'rockchip,rk3399', 'google,rk3399evb-rev2'] is not valid under any of the given schemas 'google,rk3399evb-rev2' was a no longer used variant for Google. The binding only mentions 'rockchip,rk3399-evb', 'rockchip,rk3399', so fix this error by removing 'google,rk3399evb-rev2' from the compatible property in rk3399-evb.dts and change it into generic rk3399-evb support only. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/rockchip.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200302092759.3291-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11arm64: dts: librem5-devkit: add lsm9ds1 mount matrixMartin Kepplinger1-0/+3
The IMU chip on the librem5-devkit is not mounted at the "natural" place that would match normal phone orientation (see the documentation for the details about what that is). Since the lsm9ds1 driver supports providing a mount matrix, we can describe the orientation on the board in the dts: Create a right-handed coordinate system (x * -1; see the datasheet for the axis) and rotate 180 degrees around the y axis because the device sits on the back side from the display. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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