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2019-03-28ARM: dts: at91: Fix typo in ISC_D0 on PC9David Engraf1-1/+1
The function argument for the ISC_D0 on PC9 was incorrect. According to the documentation it should be 'C' aka 3. Signed-off-by: David Engraf <david.engraf@sysgo.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Fixes: 7f16cb676c00 ("ARM: at91/dt: add sama5d2 pinmux") Cc: <stable@vger.kernel.org> # v4.4+
2019-03-28ARM: at91: pm: do not disable/enable PLLA for ULP modesClaudiu Beznea1-31/+0
There is no need to disable/enable PLLA when switching to one of the ULP modes. The PLLA consumers should take care of this. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: at91: pm: disable RC oscillator in ULP0Claudiu Beznea1-2/+37
Disable RC oscillator in ULP0 as datasheet specifies. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: at91: pm: add ULP1 support for SAM9X60Claudiu Beznea2-1/+64
Add ULP1 support for SAM9X60. In pm_suspend.S enable RC oscillator in PMC if it is not enabled. At resume the state before suspend is restored. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: at91: pm: add support for per SoC wakeup source configurationClaudiu Beznea1-8/+34
Add support for per SoC wakeup source configuration. In this way we could have per SoC wakeup sources, shutdown controller and power management controller configurations for ULP1 power management mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: at91: pm: keep at91_pm_backup_init() only for SAMA5D2 SoCsClaudiu Beznea1-0/+3
In at91_pm_backup_init() return if it is not about SAMA5D2 SoCs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: at91: pm: initial PM support for SAM9X60Claudiu Beznea3-0/+34
Add initial PM support for SAM9X60. This include idle, WFI and ULP0. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: at91: pm: introduce at91_soc_pm structureClaudiu Beznea1-56/+62
To have per SoC PM information add a new structure which embed a member of type struct at91_pm_data. This will allow easy addition of new information without contaminate struct at91_pm_data that is passed to the last phase suspend function (at91_suspend_sram_fn). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: dts: at91: sama5d2_xplained: Add proper regulator states for suspend-to-memBoris Brezillon1-0/+54
When entering suspend-to-mem, all PMIC outputs are disabled except VDDIODDR which is put in power saving mode, and whose voltage is increased (probably to counter the poor accuracy of power saving mode). Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [claudiu.beznea@microchip.com: use regulator-changeable-in-suspend, regulator-suspend-max-microvolt, regulator-suspend-max-microvolt, use macros for regulators' states, add regulator-inital-state] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: dts: at91: sama5d2: add labels to soc dtsi for derivative boardsNicolas Ferre1-3/+3
This adds labels to commonly used device-tree nodes so that derivative boards can avoid ahb/apb hierarchy. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-27ARM: dts: rockchip: Add device tree for rk3288-veyron-mightyDouglas Anderson2-0/+35
Mighty is basically the same Chromebook as Jaq but it has a full-sized SD slot and some different (slightly more rugged) plastics around it. Like Jaq, Mighty may show up with various different brandings but all of them have the same board inside. In the downstream kernel Mighty and Jaq share a "dtsi" and Mighty just adds the SD write protect (needed for a full-sized SD slot). We'll do this upstream by just including the Jaq dts and make the changes. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-27ARM: dts: rskrza1: Add remaining LEDsGeert Uytterhoeven1-1/+12
Describe the remaining 3 LEDs, which are driven by the first CAT9554 port expander. Drop the superfluous status property from the leds node while at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-27ARM: dts: rskrza1: Add I2C supportGeert Uytterhoeven1-0/+33
Enable the I2C bus, and add the following devices: - Two CAT9554 port expanders (8 GPIOs, interrupt not wired by default), - R1EX24016ASAS0A EEPROM. The bus also contains a MAX9856 Audio Codec, which is not yet supported. All devices (incl. the audio codec) are documented to support an I2C bus running at 400 kHz. Pinctrl is based on the RZ/A BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-26ARM: dts: sun7i: fix typos in uart pin muxMans Rullgard1-4/+4
The recently added uart mux options had a few typos. Fix them. Fixes: 43d0fe112585 ("ARM: dts: sun7i: add pinctrl for missing uart mux options") Reported-by: Werner Böllmann <Werner.Boellmann@fh-dortmund.de> Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: dts: sun9i: Remove deprecated pinctrl propertiesMaxime Ripard1-5/+4
We switched to the generic pinctrl binding some time ago, yet the GMAC pinctrl node apparently slipped through. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: dts: sun8i: h3: Add default dr_modeMaxime Ripard1-0/+1
The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: OMAP2+: Handle reset quirks for dynamically allocated modulesTony Lindgren4-1/+88
For dynamically allocated struct omap_hwmod data, we need to populate the device IP specific reset quirks. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: OMAP2+: Remove hwmod .rev data and use local SoC checks insteadTony Lindgren12-31/+7
We can just check for omap2 and 3 for i2c and smartreflex locally. The rest of the .rev data is already unused. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: OMAP2+: Allocate struct omap_hwmod based on dts dataTony Lindgren1-4/+78
With ti-sysc interconnect target module, we can allocate struct omap_hwmod data based on the devicetree data. This allows dropping the static SoC specific data eventually so we will only boot with data we actually need. To allocate struct omap_hwmod dynamically, we need to add a mutex for modifying the list, and remove __init for few functions. Note that we are not initialized oh->_clk or the optional clocks and their related quirks. That can be directly handled by the interconnect target module driver. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: OMAP2+: Define _HWMOD_STATE_DEFAULT and use itTony Lindgren2-6/+7
For dynamically allocated struct hwmod entries probing with ti-sysc interconnect target module driver, we need to specify the initial default state the same way as we do for the platform data cases. Let's prepare for that by adding _HWMOD_STATE_DEFAULT that we can then use to set the initial default state without a need to add similar CONFIG_PM handling in multiple places. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: OMAP2+: Prepare class allocation for dynamically allocated modulesTony Lindgren1-8/+10
For dynamically allocated sysconfig data we only need to allocate a new class for the cases where the class is shared. For dynamically allocated struct omap_hwmod we will always allocate a new class. Let's add detection for when we need to allocate a new class by comparing the class name against the module name. If they match, there's no need to allocate a new calls as we don't have case of mixed platform data and dts data initialized modules for the same class. Let's also move the init of class data inside the spinlock. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: OMAP2+: Make interconnect target module allocation functions staticTony Lindgren1-14/+16
Only omap_hwmod_init_module() gets called, the rest of the interconnect target module allocation functions can be static. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: OMAP2+: Fix potentially uninitialized return value for _setup_reset()Tony Lindgren1-1/+1
Commit 747834ab8347 ("ARM: OMAP2+: hwmod: revise hardreset behavior") made the call to _enable() conditional based on no oh->rst_lines_cnt. This caused the return value to be potentially uninitialized. Curiously we see no compiler warnings for this, probably as this gets inlined. We call _setup_reset() from _setup() and only _setup_postsetup() if the return value is zero. Currently the return value can be uninitialized for cases where oh->rst_lines_cnt is set and HWMOD_INIT_NO_RESET is not set. Fixes: 747834ab8347 ("ARM: OMAP2+: hwmod: revise hardreset behavior") Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: dts: Fix dcan clkctrl clock for am3Tony Lindgren1-2/+2
We must not use legacy clock defines for dts clckctrl clocks as the offsets will be wrong. Fixes: 87fc89ced3a7 ("ARM: dts: am335x: Move l4 child devices to probe them with ti-sysc") Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-03-26ARM: dts: imx7ulp: add ocotp supportAnson Huang1-0/+6
Add i.MX7ULP OCOTP support, its clock source is from M4 BUS clock which is NOT available in Linux clock tree, but M4 BUS clock is always ON when A7 (Linux) is alive, so just use dummy clock here. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-26ARM: dts: Add devicetree for Eckelmann ci4x10Uwe Kleine-König2-0/+382
This is one of two boards that make use of the recently introduced SIOX bus. Apart from the devices described in the dts it features a display with touch that I didn't include here because it needs some non-mainline change to operate correctly. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-26ARM: dts: stm32: add initial support of stm32mp157c-dk2 boardAlexandre Torgue2-0/+76
Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2). This board is a "super-set" of stm32mp157a-dk1. It embeds a STM32MP157c SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Same connections than stm32mp157a-dk1 board are available. Display panel (otm8009a) and Murata wifi/BT combo is added. This patch adds basic support for a kernel boot and enable otm8009a display panel. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-03-26ARM: dts: stm32: add initial support of stm32mp157a-dk1 boardAlexandre Torgue2-0/+78
Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1). This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Several connections are available on this boards: 4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ... This patch enables basic support for a kernel boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-03-25ARM: dts: sunxi: Add default dr_modeMaxime Ripard6-0/+6
The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: A23/A33: Fix pinctrl node namesMaxime Ripard1-5/+5
The NAND pinctrl nodes names don't follow the pattern we've used and enforced for some time. Make sure they do. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Remove pinctrl size-cells propertyMaxime Ripard2-2/+0
The children nodes of the pinctrl node hadn't have any reg property for quite some time, so we don't need the size-cells property. Remove it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Remove useless AHCI propertiesMaxime Ripard1-2/+0
The SATA controller never have any children nodes, so we don't need the address and size cells properties. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Fix AHCI reset-names propertyMaxime Ripard1-1/+1
The AHCI node was introduced with a typo in the reset-names property that got written resets-name instead. This was working because the reset is optional for that driver, and the controller was put out of reset by the bootloader. Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: sunxi: dts: Split USB PHY cells into an arrayMaxime Ripard3-3/+3
Even though it doesn't make any difference at the binary level, the reg property is an array of cells, and should be represented as such. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: tbs-a711: Fix typo in regulatorsMaxime Ripard1-2/+2
The regulator properties suffix is -supply, yet a _supply slipped in. This was working because the regulator framework will provide a dummy regulator when none is provided in the device tree, and the regulator itself was always enabled. Fixes: 90c5d7cdae64 ("ARM: dts: sun8i: a711: Add regulator support") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Fix the TCON output clockMaxime Ripard8-0/+11
Even though we shouldn't really have any external user of the clock provided by the TCON, if clock-output-names is set, then #clock-cells must be there as well. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: sunxi: Fix the USB PHY VBUS detect GPIO propertiesMaxime Ripard19-19/+19
While the USB PHY Device Tree mandates that the name of the VBUS detect pin should be usb0_vbus_det-gpios, a significant number of device tree use usb0_vbus_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: sunxi: Fix the USB PHY ID detect GPIO propertiesMaxime Ripard39-39/+39
While the USB PHY Device Tree mandates that the name of the ID detect pin should be usb0_id_det-gpios, a significant number of device tree use usb0_id_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Switch to new GPIOs properties for i2c-gpioMaxime Ripard2-5/+5
The i2c-gpio driver uses named gpios now and the array of GPIOs is deprecated. Switch to the new binding. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Fix GIC compatibleMaxime Ripard6-6/+6
As can be shown by the YAML schema now, the combination of GIC compatibles we were using has never been an option. Switch to the gic-400 variant, which is the more correct option. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun5i: lichee-pi one: Remove stale pinctrl-names entryMaxime Ripard1-1/+0
Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: optimus: Fix fixed-regulatorsMaxime Ripard1-2/+2
Commit 1848f3f44444 ("ARM: dts: sun9i: Remove GPIO pinctrl nodes to avoid warnings") was wrong on the optimus, and instead of droping the pinctrl-names property, it dropped the regulator-name one. Obviously, that wasn't what was intended. Reinstate regulator-name and drop pinctrl-names. Fixes: 1848f3f44444 ("ARM: dts: sun9i: Remove GPIO pinctrl nodes to avoid warnings") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a23/a33: Add R_I2C ControllerMaxime Ripard1-0/+20
The A23 and A33 both have an I2C controller in the ARISC domain, that share the same pins with the RSB bus. Even if it's an unusual configuration, that device can be used to drive the PMIC, so let's use it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a33: Add default address and size cells to the DSI nodeMaxime Ripard1-0/+2
The DSI bindings require that an address cell size of 1, and a size cell of 0. Instead of duplicating it in each and every board DTS file, let's put it in the DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: Add missing unit addressMaxime Ripard1-1/+1
The soc node in the A80 DTSI has a ranges property, but no matching unit address, which results in a DTC warning. Add the unit address to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: Fix Display Engine DTC warningsMaxime Ripard2-64/+15
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: r40: Fix Display Engine DTC warningsMaxime Ripard1-4/+1
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a83t: Fix Display Engine DTC warningsMaxime Ripard2-4/+1
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: v3s: Fix Display Engine DTC warningsMaxime Ripard1-8/+2
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun8i: a23/a33: Fix Display Engine DTC warningsMaxime Ripard6-63/+29
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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