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2021-10-25ARM: 9148/1: handle CONFIG_CPU_ENDIAN_BE32 in arch/arm/kernel/head.SLABBE Corentin1-2/+2
My intel-ixp42x-welltech-epbx100 no longer boot since 4.14. This is due to commit 463dbba4d189 ("ARM: 9104/2: Fix Keystone 2 kernel mapping regression") which forgot to handle CONFIG_CPU_ENDIAN_BE32 as possible BE config. Suggested-by: Krzysztof Hałasa <khalasa@piap.pl> Fixes: 463dbba4d189 ("ARM: 9104/2: Fix Keystone 2 kernel mapping regression") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2021-10-25irq: arm: perform irqentry in entry codeMark Rutland3-11/+9
In preparation for removing HANDLE_DOMAIN_IRQ_IRQENTRY, have arch/arm perform all the irqentry accounting in its entry code. For configurations with CONFIG_GENERIC_IRQ_MULTI_HANDLER, we can use generic_handle_arch_irq(). Other than asm_do_IRQ(), all C calls to handle_IRQ() are from irqchip handlers which will be called from generic_handle_arch_irq(), so to avoid double accounting IRQ entry, the entry logic is moved from handle_IRQ() into asm_do_IRQ(). For ARMv7M the entry assembly is tightly coupled with the NVIC irqchip, and while the entry code should logically live under arch/arm/, moving the entry logic there makes things more convoluted. So for now, place the entry logic in the NVIC irqchip, but separated into a separate function to make the split of responsibility clear. For all other configurations without CONFIG_GENERIC_IRQ_MULTI_HANDLER, IRQ entry is already handled in arch code, and requires no changes. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M Cc: Russell King <linux@armlinux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
2021-10-25irq: add a (temporary) CONFIG_HANDLE_DOMAIN_IRQ_IRQENTRYMark Rutland1-0/+1
Going forward we want architecture/entry code to perform all the necessary work to enter/exit IRQ context, with irqchip code merely handling the mapping of the interrupt to any handler(s). Among other reasons, this is necessary to consistently fix some longstanding issues with the ordering of lockdep/RCU/tracing instrumentation which many architectures get wrong today in their entry code. Importantly, rcu_irq_{enter,exit}() must be called precisely once per IRQ exception, so that rcu_is_cpu_rrupt_from_idle() can correctly identify when an interrupt was taken from an idle context which must be explicitly preempted. Currently handle_domain_irq() calls rcu_irq_{enter,exit}() via irq_{enter,exit}(), but entry code needs to be able to call rcu_irq_{enter,exit}() earlier for correct ordering across lockdep/RCU/tracing updates for sequences such as: lockdep_hardirqs_off(CALLER_ADDR0); rcu_irq_enter(); trace_hardirqs_off_finish(); To permit each architecture to be converted to the new style in turn, this patch adds a new CONFIG_HANDLE_DOMAIN_IRQ_IRQENTRY selected by all current users of HANDLE_DOMAIN_IRQ, which gates the existing behaviour. When CONFIG_HANDLE_DOMAIN_IRQ_IRQENTRY is not selected, handle_domain_irq() requires entry code to perform the irq_{enter,exit}() work, with an explicit check for this matching the style of handle_domain_nmi(). Subsequent patches will: 1) Add the necessary IRQ entry accounting to each architecture in turn, dropping CONFIG_HANDLE_DOMAIN_IRQ_IRQENTRY from that architecture's Kconfig. 2) Remove CONFIG_HANDLE_DOMAIN_IRQ_IRQENTRY once it is no longer selected. 3) Convert irqchip drivers to consistently use generic_handle_domain_irq() rather than handle_domain_irq(). 4) Remove handle_domain_irq() and CONFIG_HANDLE_DOMAIN_IRQ. ... which should leave us with a clear split of responsiblity across the entry and irqchip code, making it possible to perform additional cleanups and fixes for the aforementioned longstanding issues with entry code. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de>
2021-10-24ARM: dts: qcom: fix typo in IPQ8064 thermal-sensor nodeDavid Heidelberg1-1/+1
I added the missing dash inside the thermal-sensor-cells. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020203723.233578-1-david@ixit.cz
2021-10-24ARM: dts: qcom: fix thermal zones namingDavid Heidelberg4-26/+26
Rename thermal zones according to dt-schema. Fix warnings like: arch/arm/boot/dts/qcom-apq8064-cm-qs600.dt.yaml: thermal-zones: 'cpu-thermal0', 'cpu-thermal1', 'cpu-thermal2', 'cpu-thermal3' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020180002.195467-1-david@ixit.cz
2021-10-24kbuild: use more subdir- for visiting subdirectories while cleaningMasahiro Yamada2-4/+3
Documentation/kbuild/makefiles.rst suggests to use "archclean" for cleaning arch/$(SRCARCH)/boot/, but it is not a hard requirement. Since commit d92cc4d51643 ("kbuild: require all architectures to have arch/$(SRCARCH)/Kbuild"), we can use the "subdir- += boot" trick for all architectures. This can take advantage of the parallel option (-j) for "make clean". I also cleaned up the comments in arch/$(SRCARCH)/Makefile. The "archdep" target no longer exists. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
2021-10-23ARM: dts: qcom: fix flash node naming for RB3011David Heidelberg1-1/+1
rename node to comply with dt-schema Fix warning: arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml: s25fl016k@0: $nodename:0: 's25fl016k@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020204145.235050-1-david@ixit.cz
2021-10-23ARM: dts: qcom: correct mmc node namingDavid Heidelberg12-30/+30
MMC nodes has to be named mmc@ to comply with dt-bindings. Fix warnings as: arch/arm/boot/dts/qcom-msm8660-surf.dt.yaml: sdcc@12400000: $nodename:0: 'sdcc@12400000' does not match '^mmc(@.*)?$' From schema: Documentation/devicetree/bindings/mmc/arm,pl18x.yaml Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020201440.229196-1-david@ixit.cz
2021-10-23ARM: dts: qcom: fix memory and mdio nodes naming for RB3011David Heidelberg1-3/+3
Fixes warnings regarding to memory and mdio nodes and apply new naming following dt-schema. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020214741.261509-1-david@ixit.cz
2021-10-23ARM: dts: ipq4019-ap.dk01.1-c1: add device compatible in the dtsDavid Heidelberg2-2/+1
Version dk01.1-c1 didn't have compatible specified, which was causing dt-schema validation warnings. Remove duplicated and useless board compatible from dtsi between board and device. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211009193102.76852-2-david@ixit.cz
2021-10-23ARM: dts: qcom: apq8026-lg-lenok: rename board vendorLuca Weiss2-2/+2
In order to avoid having prefixes for multiple internal divisions of LG use the "lg" prefix instead of "lge". Fixes: ad3f04b7bef6 ("ARM: dts: qcom: Add support for LG G Watch R") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928203815.77175-2-luca@z3ntu.xyz
2021-10-23ARM: dts: qcom: sdx55: Drop '#clock-cells' from QMP PHY nodeShawn Guo1-1/+0
'#clock-cells' is a required property of QMP PHY child node, not itself. Drop it to fix the dtbs_check warnings below. qcom-sdx55-t55.dt.yaml: phy@ff6000: '#clock-cells' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' qcom-sdx55-mtp.dt.yaml: phy@ff6000: '#clock-cells' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' qcom-sdx55-telit-fn980-tlb.dt.yaml: phy@ff6000: '#clock-cells' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210929034253.24570-11-shawn.guo@linaro.org
2021-10-23ARM: dts: qcom: msm8916-samsung-serranove: Include dts from arm64Stephan Gerhold2-0/+4
After adding all necessary support for MSM8916 SMP/cpuidle without PSCI on ARM32, build the Samsung Galaxy S4 Mini VE device tree from the arm64 tree together with the ARM32 include to allow booting this device on ARM32. The approach to include device tree files from other architectures is inspired from e.g. the Raspberry Pi (bcm2711-rpi-4-b.dts) where this is used to build the device tree for both ARM32 and ARM64. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-15-stephan@gerhold.net
2021-10-23ARM: dts: qcom: msm8916: Add include for SMP without PSCI on ARM32Stephan Gerhold1-0/+62
Add a special device tree include for MSM8916 on ARM32 that sets up SMP and cpuidle without PSCI. This is meant for devices with signed firmware that does not support PSCI and only allows booting ARM32 kernels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-14-stephan@gerhold.net
2021-10-23ARM: qcom: Add ARCH_MSM8916 for MSM8916 on ARM32Stephan Gerhold1-0/+10
Add a CONFIG_ARCH_MSM8916 option to enable building MSM8916 support on ARM32. Note that since ARM64 is the main supported architecture for MSM8916 this is only intended for testing and for devices where signed firmware does not allow booting ARM64 kernels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-7-stephan@gerhold.net
2021-10-23ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226Stephan Gerhold1-0/+1
Unfortunately, some MSM8916 devices have signed firmware without ARM64 and PSCI support and can therefore only boot ARM32 Linux. The ARM Cortex-A53 cores should be actually booted exactly like the Cortex-A7 cores on MSM8226, so just add an alias for the existing code. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-9-stephan@gerhold.net
2021-10-23ARM: dts: qcom: mdm9615: fix memory node for Sierra Wireless WP8548David Heidelberg1-1/+1
Specify unit address for the memory node, to match the reg. Signed-off-by: David Heidelberg <david@ixit.cz> [bjorn: Rewrote commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020234431.298310-1-david@ixit.cz
2021-10-22Merge tag 'aspeed-5.16-devicetree-2' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dtArnd Bergmann7-1246/+470
ASPEED device tree updates for 5.16, round 2 - New machines: * Inventec Transformers, an x86 family server with an AST2600 BMC - Updates to the Everest and Rainier sensors, gpios and KCS devices - New UART routing device tree description * tag 'aspeed-5.16-devicetree-2' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: Add uart routing to device tree ARM: dts: aspeed: rainier: Enable earlycon ARM: dts: aspeed: rainier: Add front panel LEDs ARM: dts: aspeed: rainier: Add 'factory-reset-toggle' as GPIOF6 ARM: dts: aspeed: rainier: Remove PSU gpio-keys ARM: dts: aspeed: rainier: Remove gpio hog for GPIOP7 ARM: dts: aspeed: rainier: Add eeprom on bus 12 ARM: dts: aspeed: p10bmc: Enable KCS channel 2 ARM: dts: aspeed: p10bmc: Use KCS 3 for MCTP binding ARM: dts: aspeed: Adding Inventec Transformers BMC ARM: dts: aspeed: everest: Fix bus 15 muxed eeproms ARM: dts: aspeed: everest: Add IBM Operation Panel I2C device ARM: dts: aspeed: everest: Add I2C switch on bus 8 ARM: dts: aspeed: rainier and everest: Remove PCA gpio specification ARM: dts: aspeed: p10bmc: Fix ADC iio-hwmon battery node name Link: https://lore.kernel.org/r/CACPK8Xd=eAMk-S3akhGgL4i_K190Nz9t=_CrdHQMJ+nbW172mg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-22ARM: Recover kretprobe modified return address in stacktraceMasami Hiramatsu4-0/+28
Since the kretprobe replaces the function return address with the kretprobe_trampoline on the stack, arm unwinder shows it instead of the correct return address. This finds the correct return address from the per-task kretprobe_instances list and verify it is in between the caller fp and callee fp. Note that this supports both GCC and clang if CONFIG_FRAME_POINTER=y and CONFIG_ARM_UNWIND=n. For the ARM unwinder, this is still not working correctly. Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2021-10-22ARM: kprobes: Make a frame pointer on __kretprobe_trampolineMasami Hiramatsu1-4/+24
Currently kretprobe on ARM just fills r0-r11 of pt_regs, but that is not enough for the stacktrace. Moreover, from the user kretprobe handler, stacktrace needs a frame pointer on the __kretprobe_trampoline. This adds a frame pointer on __kretprobe_trampoline for both gcc and clang case. Those have different frame pointer so we need different but similar stack on pt_regs. Gcc makes the frame pointer (fp) to point the 'pc' address of the {fp, ip (=sp), lr, pc}, this means {r11, r13, r14, r15}. Thus if we save the r11 (fp) on pt_regs->r12, we can make this set on the end of pt_regs. On the other hand, Clang makes the frame pointer to point the 'fp' address of {fp, lr} on stack. Since the next to the pt_regs->lr is pt_regs->sp, I reused the pair of pt_regs->fp and pt_regs->ip. So this stores the 'lr' on pt_regs->ip and make the fp to point pt_regs->fp. For both cases, saves __kretprobe_trampoline address to pt_regs->lr, so that the stack tracer can identify this frame pointer has been made by the __kretprobe_trampoline. Note that if the CONFIG_FRAME_POINTER is not set, this keeps fp as is. Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2021-10-22ARM: clang: Do not rely on lr register for stacktraceMasami Hiramatsu1-2/+1
Currently the stacktrace on clang compiled arm kernel uses the 'lr' register to find the first frame address from pt_regs. However, that is wrong after calling another function, because the 'lr' register is used by 'bl' instruction and never be recovered. As same as gcc arm kernel, directly use the frame pointer (r11) of the pt_regs to find the first frame address. Note that this fixes kretprobe stacktrace issue only with CONFIG_UNWINDER_FRAME_POINTER=y. For the CONFIG_UNWINDER_ARM, we need another fix. Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2021-10-22dts: socfpga: Add Mercury+ AA1 devicetreePaweł Anikiel2-0/+113
Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211021151736.2096926-2-pan@semihalf.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-22ARM: dts: spear13xx: Drop malformed 'interrupt-map' on PCI nodesRob Herring2-8/+0
The spear13xx PCI 'interrupt-map' property is not parse-able. '#interrupt-cells' is missing and there are 3 #address-cells. Based on the driver, the only supported interrupt is for MSI. Therefore, 'interrupt-map' is not needed. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211022141156.2592221-1-robh@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-21Merge tag 'aspeed-5.16-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/defconfigsArnd Bergmann2-13/+23
ASPEED defconfig updates for 5.16 - Add options that are enabled in the common OpenBMC kernel - Re-enable DRM_FBDEV_EMULATION - Turn on the various sensor drivers that are used in BMC systems, so we can boot test where they are modelled in Qemu * tag 'aspeed-5.16-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: configs: aspeed: Remove unused USB gadget devices ARM: config: aspeed: Enable Network Block Device ARM: configs: aspeed: Enable pstore and lockup detectors ARM: configs: aspeed: Enable commonly used drivers ARM: configs: aspeed: Disable IPV6 SIT device ARM: configs: aspeed_g5: Reneable DRM_FBDEV_EMULATION Link: https://lore.kernel.org/r/CACPK8Xd0mVn2Cy7d=VBTDMpU=WHrftsiihwH224ekFSDGKAbyA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-21ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ceClaudiu Beznea1-0/+12
Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality. PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be used as a fallback only in case PIT64B will fail to probe. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-4-claudiu.beznea@microchip.com
2021-10-21ARM: dts: at91: sama7g5: add tcb nodesClaudiu Beznea1-0/+20
Add TCB nodes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-3-claudiu.beznea@microchip.com
2021-10-21ARM: dts: at91: sama7g5: add rtc nodeEugen Hristev1-0/+7
Add RTC node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers compared with sam9x60] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-2-claudiu.beznea@microchip.com
2021-10-21ARM: dts: aspeed: Add uart routing to device treeChia-Wei Wang3-0/+18
Add LPC uart routing to the device tree for Aspeed SoCs. Signed-off-by: Oskar Senft <osk@google.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Tested-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20210927023053.6728-6-chiawei_wang@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Enable earlyconJoel Stanley1-1/+1
Rainier was missed when enabling all of the other machines in commit 239566b032f3 ("ARM: dts: aspeed: Set earlycon boot argument"). Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add front panel LEDsJoel Stanley1-0/+42
These were meant to be part of commit 4fb27b3f9176 ("ARM: dts: aspeed: rainier: Add system LEDs") but went missing. Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add 'factory-reset-toggle' as GPIOF6Isaac Kurth1-1/+1
The state of this GPIO determines whether a factory reset has been requested. If a physical switch is used, it can be high or low. During boot, the software checks and records the state of this switch. If it is different than the previous recorded state, then the read-write portions of memory are reformatted. Signed-off-by: Isaac Kurth <isaac.kurth@ibm.com> Reviewed-by: Adriana Kobylak <anoo@us.ibm.com> Link: https://lore.kernel.org/r/20210714214741.1547052-1-blisaac91@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Remove PSU gpio-keysB. J. Wyman1-28/+0
Remove the gpio-keys entries for the power supply presence lines from the Rainier device tree. The user space applications are going to change from using libevdev to libgpiod. Signed-off-by: B. J. Wyman <bjwyman@gmail.com> Link: https://lore.kernel.org/r/20210623230401.3050076-1-bjwyman@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Remove gpio hog for GPIOP7Eddie James1-7/+0
Only the pass 1 Ingraham board (Rainier system) had a micro-controller wired to GPIOP7 on ball Y23. Pass 2 boards have this ball wired to the heartbeat LED, so remove the hog as this device tree supports pass 2. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210915214738.34382-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add eeprom on bus 12Eddie James1-0/+5
The devicetree was missing an eeprom. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210915214738.34382-4-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Enable KCS channel 2Andrew Jeffery2-0/+10
Rainier uses KCS channel 2 as the source for the debug-trigger application outlined at [1] and implemented at [2]. [1] https://github.com/openbmc/docs/blob/master/designs/bmc-service-failure-debug-and-recovery.md [2] https://github.com/openbmc/debug-trigger Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210623033854.587464-8-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Use KCS 3 for MCTP bindingAndrew Jeffery2-5/+12
The MCTP LPC driver was loaded by hacking up the compatible in the devicetree node for KCS 4. With the introduction of the raw KCS driver this hack is no-longer required. Use the regular compatible string for KCS 4 and configure the appropriate SerIRQ. The reset state of the status bits on KCS 4 is inappropriate for the MCTP LPC binding. Switch to KCS 3 which has a different reset behaviour. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: Adding Inventec Transformers BMCLin.TommySC 林世欽 TAO2-0/+329
Initial introduction of Inventec Transformers x86 family equipped with AST2600 BMC SoC. Signed-off-by: Tommy Lin <Lin.TommySC@inventec.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/7d7b20575f994a3c9018223a3c5f198d@inventec.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Fix bus 15 muxed eepromsEddie James1-20/+20
The eeproms on bus 15 muxes were at the wrong addresses. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-6-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Add IBM Operation Panel I2C deviceEddie James1-1/+7
Set I2C bus 14 to multi-master mode and add the panel device that will register the I2C controller as a slave device. In addition, in early Everest systems, the panel device was behind an I2C switch, which doesn't work for slave mode. Get it working (albeit unreliably, since a master transaction might switch the switch at any moment) by defaulting the switch channel to the one with the panel. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Add I2C switch on bus 8Eddie James1-0/+23
The switch controls two busses containing some VRMs. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-4-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier and everest: Remove PCA gpio specificationEddie James2-1181/+0
Specifying gpio nodes under PCA led controllers no longer does anything, so remove those nodes in the device trees. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-3-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Fix ADC iio-hwmon battery node nameEddie James2-2/+2
In keeping with previous systems, call the iio-hwmon bridge node "iio-hwmon-battery" to distinguish it as the battery voltage sensor. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-2-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-20Merge tag 'imx-defconfig-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfigsArnd Bergmann1-29/+18
i.MX defconfig update for 5.16: - A series from Marcel Ziswiler to update imx_v6_v7_defconfig for the new Colibri iMX6ULL eMMC variant support. - Enable HID I2C in the imx_v6_v7_defconfig as it is used for a HID compliant wacom device on the reMarkable2 tablet. * tag 'imx-defconfig-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx_v6_v7_defconfig: Enable HID I2C ARM: imx_v6_v7_defconfig: enable bpf syscall and cgroup bpf ARM: imx_v6_v7_defconfig: build imx sdma driver as module ARM: imx_v6_v7_defconfig: rebuild default configuration ARM: imx_v6_v7_defconfig: change snd soc tlv320aic3x to i2c variant ARM: imx_v6_v7_defconfig: enable mtd physmap Link: https://lore.kernel.org/r/20211016140138.1603-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'mvebu-defconfig-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/defconfigsArnd Bergmann1-10/+8
mvebu defconfig for 5.16 (part 1) Update defconfig and enable mtd physmap * tag 'mvebu-defconfig-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: mvebu_v7_defconfig: rebuild default configuration ARM: mvebu_v7_defconfig: enable mtd physmap Link: https://lore.kernel.org/r/871r4mmecw.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'sunxi-core-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/socArnd Bergmann2-6/+2
Platform core changes for the Allwinner SoCs, this time adding SPDX headers to our files. * tag 'sunxi-core-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: sunxi: Add a missing SPDX license header ARM: sunxi: Add a missing SPDX license header Link: https://lore.kernel.org/r/0ceaad3e-dc26-4be6-b98f-d25e51a41b81.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'stm32-soc-for-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/socArnd Bergmann2-0/+11
STM32 SoC for v5.16, round 1 Highlights: ---------- Add support of new STM32MP13 SoC which enhances current STM32 MPU family. It is mainly a derivative of STM32MP15 SoCs (one Cortex-A7 plus standard peripherals). The STM32MP13 SoC diversity is composed by: -STM32MP131: -core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX -storage: 3*SDMCC, 1*QSPI, FMC -com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART -audio: 2*SAI -network: 1*ETH(GMAC) -STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 -STM32MP135: STM32MP133 + DCMIPP, LTDC * tag 'stm32-soc-for-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: stm32: add initial support for STM32MP13 family docs: arm: stm32: introduce STM32MP13 SoCs Link: https://lore.kernel.org/r/0b6c9657-dcca-3bad-601f-610dfc81d9ae@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'omap-for-v5.16/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dtArnd Bergmann7-12/+12
Changes for omap gpmc bindings and devicetree files for v5.16 A series of changes to update the gpmc related bindings to yaml format, and a few non-urgent dts fixes. * tag 'omap-for-v5.16/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap: fix gpmc,mux-add-data type ARM: dts: omap: Fix boolean properties gpmc,cycle2cycle-{same|diff}csen dt-bindings: memory-controllers: ti,gpmc: Convert to yaml dt-bindings: mtd: ti,gpmc-onenand: Convert to yaml dt-bindings: mtd: ti,gpmc-nand: Convert to yaml dt-bindings: memory-controllers: Introduce ti,gpmc-child dt-bindings: net: Remove gpmc-eth.txt dt-bindings: mtd: Remove gpmc-nor.txt Link: https://lore.kernel.org/r/pull-1634280279-284035@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge branch 'mstar-dt-next' of https://github.com/linux-chenxing/linux into arm/dtArnd Bergmann1-0/+9
* 'mstar-dt-next' of https://github.com/linux-chenxing/linux: ARM: dts: mstar: Mark timer with arm,cpu-registers-not-fw-configured ARM: dts: mstar: Add rtc device node Link: https://lore.kernel.org/r/20211020163010.3079-1-romain.perier@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20ARM: bcm: Removed forced select of interrupt controllersFlorian Fainelli1-4/+0
Now that the various second level interrupt controllers have been moved to IRQCHIP_PLATFORM_DRIVER and they do default to ARCH_BRCMSTB and ARCH_BCM2835 where relevant, remove their forced selection from the machine entry to allow an user to build them as modules. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211020184859.2705451-13-f.fainelli@gmail.com
2021-10-20ARM: broadcom: Use of_get_cpu_hwid()Rob Herring1-3/+3
Replace open coded parsing of CPU nodes 'reg' property with of_get_cpu_hwid(). Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211006164332.1981454-4-robh@kernel.org
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