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2022-07-08Merge tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx into arm/dtArnd Bergmann2-3/+3
ARM: Zynq DT changes for v5.20 - Align gpio-keys node names with dtschema * tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx: ARM: dts: xilinx: align gpio-key node names with dtschema Link: https://lore.kernel.org/r/87d2bd4a-b90d-6396-17c5-c95ac64d17d0@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08Merge tag 'zynq-soc-for-v5.20' of https://github.com/Xilinx/linux-xlnx into arm/socArnd Bergmann1-0/+1
ARM: Zynq SoC changes for v5.20 - Fix refcount leak in zynq_get_revision() * tag 'zynq-soc-for-v5.20' of https://github.com/Xilinx/linux-xlnx: cpufreq: zynq: Fix refcount leak in zynq_get_revision Link: https://lore.kernel.org/r/e1d0a721-afa4-93a0-7119-0e4481a0624b@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-07Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski13-19/+89
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-07ARM/dma-mapping: merge IOMMU opsRobin Murphy1-24/+13
The dma_sync_* operations are now the only difference between the coherent and non-coherent IOMMU ops. Some minor tweaks to make those safe for coherent devices with minimal overhead, and we can condense down to a single set of DMA ops. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: consolidate IOMMU ops callbacksRobin Murphy1-183/+55
Merge the coherent and non-coherent callbacks down to a single implementation each, relying on the generic dev->dma_coherent flag at the points where the difference matters. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: drop .dma_supported for IOMMU opsRobin Murphy1-23/+0
When an IOMMU is present, we trust that it should be capable of remapping any physical memory, and since the device masks represent the input (virtual) addresses to the IOMMU it makes no sense to validate them against physical PFNs anyway. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: use dma-direct unconditionallyChristoph Hellwig5-378/+19
Use dma-direct unconditionally on arm. It has already been used for some time for LPAE and nommu configurations. This mostly changes the streaming mapping implementation and the (simple) coherent allocator for device that are DMA coherent. The existing complex allocator for uncached mappings for non-coherent devices is still used as is using the arch_dma_alloc/arch_dma_free hooks. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Andre Przywara <andre.przywara@arm.com> [highbank] Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: use the generic versions of dma_to_phys/phys_to_dma by defaultChristoph Hellwig7-55/+21
Only the footbridge platforms provide their own DMA address translation helpers, so switch to the generic version for all other platforms, and consolidate the footbridge implementation to remove two levels of indirection. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: use dma_to_phys/phys_to_dma in the dma-mapping codeChristoph Hellwig1-12/+12
Use the helpers as expected by the dma-direct code in the old arm dma-mapping code to ease a gradual switch to the common DMA code. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: remove the unused virt_to_dma helperChristoph Hellwig1-9/+1
virt_to_dma was only used by the now removed dmabounce code. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: mark various dma-mapping routines static in dma-mapping.cChristoph Hellwig2-129/+46
With the dmabounce removal these aren't used outside of dma-mapping.c, so mark them static. Move the dma_map_ops declarations down a bit to avoid lots of forward declarations. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Marc Zyngier <maz@kernel.org>
2022-07-07ARM/dma-mapping: remove dmabounceChristoph Hellwig5-619/+0
Remove the now unused dmabounce code. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2022-07-07ARM: sa1100/assabet: move dmabounce hack to ohci driverArnd Bergmann2-65/+1
The sa1111 platform is one of the two remaining users of the old Arm specific "dmabounce" code, which is an earlier implementation of the generic swiotlb. Linus Walleij submitted a patch that removes dmabounce support from the ixp4xx, and I had a look at the other user, which is the sa1111 companion chip. Looking at how dmabounce is used, I could narrow it down to one driver one three machines: - dmabounce is only initialized on assabet/neponset, jornada720 and badge4, which are the platforms that have an sa1111 and support DMA on it. - All three of these suffer from "erratum #7" that requires only doing DMA to half the memory sections based on one of the address lines, in addition, the neponset also can't DMA to the RAM that is connected to sa1111 itself. - the pxa lubbock machine also has sa1111, but does not support DMA on it and does not set dmabounce. - only the OHCI and audio devices on sa1111 support DMA, but as there is no audio driver for this hardware, only OHCI remains. In the OHCI code, I noticed that two other platforms already have a local bounce buffer support in the form of the "local_mem" allocator. Specifically, TMIO and SM501 use this on a few other ARM boards with 16KB or 128KB of local SRAM that can be accessed from the OHCI and from the CPU. While this is not the same problem as on sa1111, I could not find a reason why we can't re-use the existing implementation but replace the physical SRAM address mapping with a locally allocated DMA buffer. There are two main downsides: - rather than using a dynamically sized pool, this buffer needs to be allocated at probe time using a fixed size. Without having any idea of what it should be, I picked a size of 64KB, which is between what the other two OHCI front-ends use in their SRAM. If anyone has a better idea what that size is reasonable, this can be trivially changed. - Previously, only USB transfers to unaddressable memory needed to go through the bounce buffer, now all of them do, which may impact runtime performance for USB endpoints that do a lot of transfers. On the upside, the local_mem support uses write-combining buffers, which should be a bit faster for transfers to the device compared to normal uncached coherent memory as used in dmabounce. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Christoph Hellwig <hch@infradead.org> Cc: Laurentiu Tudor <laurentiu.tudor@nxp.com> Cc: linux-usb@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Christoph Hellwig <hch@lst.de>
2022-07-07arm64: dts: renesas: Prepare AA1024XD12 panel .dtsi for overlay supportLaurent Pinchart1-39/+0
The Mitsubishi AA1024XD12 panel can be used for R-Car Gen2 and Gen3 boards as an optional external panel. It is described in the arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi file as a direct child of the DT root node. This allows including r8a77xx-aa104xd12-panel.dtsi in board device trees, with other minor modifications, to enable the panel. This is however not how external components should be modelled. Instead of modifying the board device tree to enable the panel, it should be compiled as a DT overlay, to be loaded by the boot loader. Prepare the r8a77xx-aa104xd12-panel.dtsi file for this usage by declaring a panel node only, without hardcoding its path. Overlay sources can then include r8a77xx-aa104xd12-panel.dtsi where appropriate. This change doesn't cause any regression as r8a77xx-aa104xd12-panel.dtsi is currently unused. As overlay support for this panel has only been tested with Gen3 hardware, and Gen2 support will require more development, move the file to arch/arm64/boot/dts/renesas/. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20211229193135.28767-2-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-07genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMPSamuel Holland1-1/+1
An IRQ's effective affinity can only be different from its configured affinity if there are multiple CPUs. Make it clear that this option is only meaningful when SMP is enabled. Most of the relevant code in irqdesc.c is already hidden behind CONFIG_SMP anyway. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220701200056.46555-4-samuel@sholland.org
2022-07-07Merge tag 'samsung-dt-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann4-13/+13
Samsung DTS ARM changes for v5.20, part two 1. Cleanups: align SDHCI node names. 2. DT bindings: Document preferred compatible naming schema. 3. DT bindings: fixes and improvements to Exynos PMU bindings. * tag 'samsung-dt-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: soc: samsung: exynos-pmu: add reboot-mode dt-bindings: soc: samsung: exynos-pmu: use abolute ref paths dt-bindings: soc: samsung: exynos-pmu: cleanup assigned clocks dt-bindings: samsung: document preferred compatible naming ARM: dts: s5pv210: align SDHCI node name with dtschema ARM: dts: s3c64xx: align SDHCI node name with dtschema ARM: dts: s3c24xx: align SDHCI node name with dtschema ARM: dts: exynos: align SDHCI node name with dtschema Link: https://lore.kernel.org/r/20220707080408.69251-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06ARM: 9214/1: alignment: advance IT state after emulating Thumb instructionArd Biesheuvel3-25/+30
After emulating a misaligned load or store issued in Thumb mode, we have to advance the IT state by hand, or it will get out of sync with the actual instruction stream, which means we'll end up applying the wrong condition code to subsequent instructions. This might corrupt the program state rather catastrophically. So borrow the it_advance() helper from the probing code, and use it on CPSR if the emulated instruction is Thumb. Cc: <stable@vger.kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9213/1: Print message about disabled Spectre workarounds only onceDmitry Osipenko1-2/+1
Print the message about disabled Spectre workarounds only once. The message is printed each time CPU goes out from idling state on NVIDIA Tegra boards, causing storm in KMSG that makes system unusable. Cc: stable@vger.kernel.org Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9212/1: domain: Modify Kconfig help textLinus Walleij1-1/+5
After the removal of set_fs() the reference to set_fs() is stale. Alter the helptext to reflect what the config option really does. Fixes: 8ac6f5d7f84b ("ARM: 9113/1: uaccess: remove set_fs() implementation") Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9211/1: domain: drop modify_domain()Linus Walleij1-13/+0
This function/macro isn't used anywhere in the kernel. The only user was set_fs() and was deleted in the set_fs() removal patch set. Fixes: 8ac6f5d7f84b ("ARM: 9113/1: uaccess: remove set_fs() implementation") Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9210/1: Mark the FDT_FIXED sections as shareableZhen Lei2-1/+15
commit 7a1be318f579 ("ARM: 9012/1: move device tree mapping out of linear region") use FDT_FIXED_BASE to map the whole FDT_FIXED_SIZE memory area which contains fdt. But it only reserves the exact physical memory that fdt occupied. Unfortunately, this mapping is non-shareable. An illegal or speculative read access can bring the RAM content from non-fdt zone into cache, PIPT makes it to be hit by subsequently read access through shareable mapping(such as linear mapping), and the cache consistency between cores is lost due to non-shareable property. |<---------FDT_FIXED_SIZE------>| | | ------------------------------- | <non-fdt> | <fdt> | <non-fdt> | ------------------------------- 1. CoreA read <non-fdt> through MT_ROM mapping, the old data is loaded into the cache. 2. CoreB write <non-fdt> to update data through linear mapping. CoreA received the notification to invalid the corresponding cachelines, but the property non-shareable makes it to be ignored. 3. CoreA read <non-fdt> through linear mapping, cache hit, the old data is read. To eliminate this risk, add a new memory type MT_MEMORY_RO. Compared to MT_ROM, it is shareable and non-executable. Here's an example: list_del corruption. prev->next should be c0ecbf74, but was c08410dc kernel BUG at lib/list_debug.c:53! ... ... PC is at __list_del_entry_valid+0x58/0x98 LR is at __list_del_entry_valid+0x58/0x98 psr: 60000093 sp : c0ecbf30 ip : 00000000 fp : 00000001 r10: c08410d0 r9 : 00000001 r8 : c0825e0c r7 : 20000013 r6 : c08410d0 r5 : c0ecbf74 r4 : c0ecbf74 r3 : c0825d08 r2 : 00000000 r1 : df7ce6f4 r0 : 00000044 ... ... Stack: (0xc0ecbf30 to 0xc0ecc000) bf20: c0ecbf74 c0164fd0 c0ecbf70 c0165170 bf40: c0eca000 c0840c00 c0840c00 c0824500 c0825e0c c0189bbc c088f404 60000013 bf60: 60000013 c0e85100 000004ec 00000000 c0ebcdc0 c0ecbf74 c0ecbf74 c0825d08 ... ... < next prev > (__list_del_entry_valid) from (__list_del_entry+0xc/0x20) (__list_del_entry) from (finish_swait+0x60/0x7c) (finish_swait) from (rcu_gp_kthread+0x560/0xa20) (rcu_gp_kthread) from (kthread+0x14c/0x15c) (kthread) from (ret_from_fork+0x14/0x24) The faulty list node to be deleted is a local variable, its address is c0ecbf74. The dumped stack shows that 'prev' = c0ecbf74, but its value before lib/list_debug.c:53 is c08410dc. A large amount of printing results in swapping out the cacheline containing the old data(MT_ROM mapping is read only, so the cacheline cannot be dirty), and the subsequent dump operation obtains new data from the DDR. Fixes: 7a1be318f579 ("ARM: 9012/1: move device tree mapping out of linear region") Suggested-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: 9209/1: Spectre-BHB: avoid pr_info() every time a CPU comes out of idleArd Biesheuvel1-3/+3
Jon reports that the Spectre-BHB init code is filling up the kernel log with spurious notifications about which mitigation has been enabled, every time any CPU comes out of a low power state. Given that Spectre-BHB mitigations are system wide, only a single mitigation can be enabled, and we already print an error if two types of CPUs coexist in a single system that require different Spectre-BHB mitigations. This means that the pr_info() that describes the selected mitigation does not need to be emitted for each CPU anyway, and so we can simply emit it only once. In order to clarify the above in the log message, update it to describe that the selected mitigation will be enabled on all CPUs, including ones that are unaffected. If another CPU comes up later that is affected and requires a different mitigation, we report an error as before. Fixes: b9baf5c8c5c3 ("ARM: Spectre-BHB workaround") Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-07-06ARM: dts: qcom: msm8974: rename GPU's OPP table nodeDmitry Baryshkov1-1/+1
Rename the GPU's opp table node to make it follow the display/msm/gpu.yaml schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-6-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: apq8064: disable DSI and DSI PHY by defaultDmitry Baryshkov1-0/+3
Disable DSI and DSI PHY devices by default. The only actual user, Nexus 7, already contains `status = "okay"` property in the respective devices nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-5-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: apq8064: rename DSI PHY iface clockDmitry Baryshkov1-1/+1
Follow the usual scheme and use name 'iface' rather than 'iface_clk' for the interface clock. The DSI PHY driver can cope with both of them, so there is no breakage. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-4-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: extend scm compatible to match dt-schemaDavid Heidelberg4-4/+4
First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626183247.142776-1-david@ixit.cz
2022-07-06Merge tag 'dt-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dtArnd Bergmann91-348/+301
Cleanup of ARM DTS for v5.20, part two Series of cleanups for ARM DTS - white-spaces, gpio-key subnode names and gpio-key properties for more boards: TI, Marvell, AT91 and Aspeed. * tag 'dt-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: aspeed: correct gpio-keys properties ARM: dts: aspeed: align gpio-key node names with dtschema ARM: dts: at91: drop unneeded status from gpio-keys ARM: dts: at91: correct gpio-keys properties ARM: dts: at91: align gpio-key node names with dtschema ARM: dts: omap: correct gpio-keys properties ARM: dts: omap: align gpio-key node names with dtschema ARM: dts: marvell: correct gpio-keys properties ARM: dts: marvell: align gpio-key node names with dtschema ARM: dts: omap: adjust whitespace around '=' ARM: dts: ti: adjust whitespace around '=' Link: https://lore.kernel.org/r/20220706163754.33064-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dtArnd Bergmann24-109/+772
STM32 DT for v5.20, round 1 Highlights: ---------- - MCU: -Fix whitespace coding style. No functional changes. - MPU: - General: - Remove specific IPCC wakeup interrupt on STM32MP15. - Enable OPTEE firmware and scmi support (clock/reset) on STM32MP13. It allows to enable RCC clock driver. - Add new pins configurations groups. - DH boards: - Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN, uSD, USB, eMMC and SDIO wifi. - Add ST MIPID02 bindings to AV96 (not enabled by default) - OSD32: - Correct vcc-supply for eeprom. - fix missing internally connected voltage regulator (ldo3 supplied by vdd_ddr). * tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits) ARM: dts: stm32: Add ST MIPID02 bindings to AV96 ARM: dts: stm32: Add alternate pinmux for RCC pin ARM: dts: stm32: Add alternate pinmux for DCMI pins ARM: dts: stm32: Add DHCOR based DRC Compact board ARM: dts: stm32: Add alternate pinmux for UART5 pins ARM: dts: stm32: Add alternate pinmux for UART4 pins ARM: dts: stm32: Add alternate pinmux for UART3 pins ARM: dts: stm32: Add alternate pinmux for SPI2 pins ARM: dts: stm32: Add alternate pinmux for CAN1 pins dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk ARM: dts: stm32: add RCC on STM32MP13x SoC family ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 dt-bindings: rcc: stm32: select the "secure" path for stm32mp13 ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32 ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1 ARM: dts: stm32: adjust whitespace around '=' on MCU boards ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 ... Link: https://lore.kernel.org/r/a250f32b-f67c-2922-0748-e39dc791e95c@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dtArnd Bergmann18-37/+66
AT91 DT for v5.20 It contains: - compilation warning fixes for SAMA5D2 - updates for all AT91 device tree to use generic name for reset controller - reset controller node for SAMA7G5 - MCAN1 and UDPHS nodes for LAN966 SoCs - Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope with reality * tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: lan966x: Add UDPHS support dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings. ARM: dts: lan966x: Add mcan1 node. ARM: dts: at91: sama7g5: add reset-controller node ARM: dts: at91: use generic name for reset controller ARM: dts: at91: sama5d2: fix compilation warning ARM: dts: at91: sama5d2: fix compilation warning Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dtArnd Bergmann4-11/+6
Ux500 DTS updates for the v5.20 kernel: - Fix orientation matrices on a few U8500 mobile phones. - Drop unused i2c power supply handled by the power domain. * tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Drop unused i2c power domain supply ARM: dts: ux500: Fix Gavini accelerometer mounting matrix ARM: dts: ux500: Fix Codina accelerometer mounting matrix ARM: dts: ux500: Fix Janice accelerometer mounting matrix Link: https://lore.kernel.org/r/CACRpkdY1MG=HG+tOCmD1_LEAStV1-ycCLkwShMRD4R=4jGDYHQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dtArnd Bergmann23-44/+60
NFC flash node on rk3066a-mk808 and some dts styling fixes (alignment and node names). * tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: correct gpio-keys properties on rk3288-tinker ARM: dts: rockchip: align gpio-key node names with dtschema ARM: dts: rockchip: adjust whitespace around '=' ARM: dts: rockchip: enable nfc node in rk3066a-mk808.dts Link: https://lore.kernel.org/r/14795241.VsHLxoZxqI@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.19-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixesArnd Bergmann1-2/+5
Add a missing of_node_put in suspend code error path. * tag 'v5.19-rockchip-socfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: rockchip: Add missing of_node_put() in rockchip_suspend_init() Link: https://lore.kernel.org/r/7527945.6fTUFtlzNn@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-05context_tracking: Take idle eqs entrypoints over RCUFrederic Weisbecker1-2/+3
The RCU dynticks counter is going to be merged into the context tracking subsystem. Start with moving the idle extended quiescent states entrypoints to context tracking. For now those are dumb redirections to existing RCU calls. [ paulmck: Apply kernel test robot feedback. ] Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Neeraj Upadhyay <quic_neeraju@quicinc.com> Cc: Uladzislau Rezki <uladzislau.rezki@sony.com> Cc: Joel Fernandes <joel@joelfernandes.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Nicolas Saenz Julienne <nsaenz@kernel.org> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Xiongfeng Wang <wangxiongfeng2@huawei.com> Cc: Yu Liao <liaoyu15@huawei.com> Cc: Phil Auld <pauld@redhat.com> Cc: Paul Gortmaker<paul.gortmaker@windriver.com> Cc: Alex Belits <abelits@marvell.com> Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Reviewed-by: Nicolas Saenz Julienne <nsaenzju@redhat.com> Tested-by: Nicolas Saenz Julienne <nsaenzju@redhat.com>
2022-07-05ARM: dts: sun8i-r40: Add thermal trip points/cooling mapsqianfan Zhao1-0/+28
For the trip points, I used values from the BSP code. The critical trip point value is 30°C above the maximum recommended ambient temperature (85°C) for the SoC from the datasheet, so there's some headroom even at such a high ambient temperature. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-4-qianfanguijin@163.com
2022-07-05ARM: dts: sun8i-r40: add opp table for cpuqianfan Zhao6-0/+64
OPP table value is get from allwinner lichee linux-3.10 kernel driver Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-3-qianfanguijin@163.com
2022-07-05ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based boardqianfan Zhao4-0/+16
The CPU of sun8i-r40 is powered by PMIC, let's add "cpu-supply" node. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-2-qianfanguijin@163.com
2022-07-05Merge tag 'xsa-5.19-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tipLinus Torvalds1-2/+4
Pull xen security fixes from Juergen Gross: - XSA-403 (4 patches for blkfront and netfront drivers): Linux Block and Network PV device frontends don't zero memory regions before sharing them with the backend (CVE-2022-26365, CVE-2022-33740). Additionally the granularity of the grant table doesn't allow sharing less than a 4K page, leading to unrelated data residing in the same 4K page as data shared with a backend being accessible by such backend (CVE-2022-33741, CVE-2022-33742). - XSA-405 (1 patch for netfront driver, only 5.10 and newer): While adding logic to support XDP (eXpress Data Path), a code label was moved in a way allowing for SKBs having references (pointers) retained for further processing to nevertheless be freed. - XSA-406 (1 patch for Arm specific dom0 code): When mapping pages of guests on Arm, dom0 is using an rbtree to keep track of the foreign mappings. Updating of that rbtree is not always done completely with the related lock held, resulting in a small race window, which can be used by unprivileged guests via PV devices to cause inconsistencies of the rbtree. These inconsistencies can lead to Denial of Service (DoS) of dom0, e.g. by causing crashes or the inability to perform further mappings of other guests' memory pages. * tag 'xsa-5.19-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: xen/arm: Fix race in RB-tree based P2M accounting xen-netfront: restore __skb_queue_tail() positioning in xennet_get_responses() xen/blkfront: force data bouncing when backend is untrusted xen/netfront: force data bouncing when backend is untrusted xen/netfront: fix leaking data in shared pages xen/blkfront: fix leaking data in shared pages
2022-07-05Merge branch 'for-v5.20/aspeed-dts-cleanup' into for-v5.20/dts-cleanupKrzysztof Kozlowski15-123/+118
2022-07-05ARM: dts: aspeed: correct gpio-keys propertiesKrzysztof Kozlowski3-6/+0
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-37-krzysztof.kozlowski@linaro.org
2022-07-05ARM: dts: aspeed: align gpio-key node names with dtschemaKrzysztof Kozlowski15-117/+118
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-36-krzysztof.kozlowski@linaro.org
2022-07-05ARM: dts: stm32: Add ST MIPID02 bindings to AV96Marek Vasut1-0/+55
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT. Both the ST MIPID02 and DCMI are disabled by default, as the AV96 camera module is optional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for RCC pinMarek Vasut1-0/+15
Add another mux option for RCC pin, this is used on AV96 board for e.g. sensor clock supply. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for DCMI pinsMarek Vasut1-0/+37
Add another mux option for DCMI pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add DHCOR based DRC Compact boardMarek Vasut3-0/+353
Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART5 pinsMarek Vasut1-0/+13
Add another mux option for UART5 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART4 pinsMarek Vasut1-0/+30
Add another mux option for UART4 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART3 pinsMarek Vasut1-0/+41
Add another mux option for UART3 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for SPI2 pinsMarek Vasut1-0/+15
Add another mux option for SPI2 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for CAN1 pinsMarek Vasut1-0/+20
Add another mux option for CAN1 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15Marek Vasut1-3/+3
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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