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2020-05-05ARM: dts: aspeed: tacoma: Enable the second VUARTAndrew Jeffery1-0/+4
Used by some POWER hypervisors. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Add iio-hwmon nodes for IIO devicesEddie James1-0/+10
Connect the BMP280 and DPS310 to the hwmon subsystem with iio-hwmon nodes. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Add VGA reserved memory regionJoel Stanley1-0/+5
The BMC uses reserves the top 16MB of memory for the host to use for VGA or PCIe communication. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Add gpio line namesAndrew Geissler1-0/+34
Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler <geisonator@yahoo.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Add gpio line namesJoel Stanley1-0/+33
Add names for some of the GPIOs that are used in Tacoma. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: zaius: Add gpio line namesAndrew Geissler1-4/+33
Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler <geissonator@yahoo.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: romulus: Add gpio line namesAndrew Geissler1-3/+32
Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler <geissonator@yahoo.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: witherspoon: Add gpio line namesAndrew Geissler1-0/+34
Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler <geissonator@yahoo.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600: Set arch timer always-onEddie James1-0/+2
According to ASPEED, FTTMR010 is not intended to be used in the AST2600. The arch timer should be used, but Linux doesn't enable high-res timers without being assured that the arch timer is always on, so set that property in the devicetree. The FTTMR010 device is described by set to disabled. This fixes highres timer support for AST2600. Fixes: 2ca5646b5c2f ("ARM: dts: aspeed: Add AST2600 and EVB") Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Add GPIOs for FSIJoel Stanley1-6/+3
GPIO Q7 is no longer used for air/water. It is repurposed on Tacoma to indicate internal FSI (low) vs cabled (high). GPIO B0 controls the muxing of FSI to the cable (low) or internal pins (high). Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: mihawk: Change the name of ledsBen Pai1-14/+3
Change the name of power, fault and rear-id. Remove the two leds. Signed-off-by: Ben Pai <Ben_Pai@wistron.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Remove regulatorsMatthew Barth1-60/+0
Regulators will be dynamically configured and monitored from userspace. Signed-off-by: Matthew Barth <msbarth@linux.ibm.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Jim Wright <wrightj@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Add host FSI descriptionJoel Stanley1-0/+82
This adds the description of the Power CPUs that are attached to the BMC. Without this userspace will see the '/dev/scom66' style layout. Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600evb: Enable FSI masterJoel Stanley1-0/+4
Use the first FSI master. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Add gpio-key definitionsEddie James1-0/+59
Add gpio-keys for various signals on Tacoma. Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Set PCA9552 pin typesMatthew Barth1-0/+17
All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type GPIO. Signed-off-by: Matthew Barth <msbarth@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: rainier: Enable VUART2Andrew Jeffery1-0/+4
The second VUART is used to expose multiplexed, non-hypervisor consoles. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2400: Add video engine supportAlexander Filippov1-0/+10
Add a node to describe the video engine on AST2400. These changes were copied from aspeed-g5.dtsi Signed-off-by: Alexander Filippov <a.filippov@yadro.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tacoma: Enable eMMC controllerGuenter Roeck1-0/+4
Enabling emmc without enabling its controller doesn't do any good. Enable its controller as well to make it work. Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tiogapass: Add gpio line namesVijay Khemka1-0/+63
Added GPIO line names for all gpio used in tiogapass platform, these line names will be used by libgpiod to control GPIOs Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: tiogapass: Add IPMB deviceVijay Khemka1-0/+11
Adding IPMB devices for facebook tiogapass platform. Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600: Add Video Engine nodeJae Hyun Yoo1-0/+10
The AST2600 has Video Engine so add it. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2600: Add SCU interrupt controllersEddie James1-0/+16
Add nodes for the interrupt controllers provided by the SCU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-05ARM: dts: aspeed: ast2500: Add SCU interrupt controllerEddie James1-0/+8
Add a node for the interrupt controller provided by the SCU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-05-04ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridgesSteffen Trumtrar1-0/+14
Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-05-04ARM: dts: socfgpa: set bridges status to disabledSteffen Trumtrar1-0/+2
The hps-to-fpga bridges can't be used, when the FPGA is not programmed. Set the default state to disabled and leave enabling them to the board-specific dts files. Although this changes behavior, there are no in-tree users of the bridges, so this won't break anything. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-05-04ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boardsJonathan Bakker1-0/+18
Make sure that the GPIOs are configured correctly for the interrupt (otherwise it won't fire) and disable the pulls on the DVS GPIOs which are outputs. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Correct FIMC definitionsJonathan Bakker1-4/+7
The extended mainscaler is only available on FIMC1 and there are minimum pixel alignments that differ from the default. Additionally, the cam-if interface is available on all three while FIMC2 has no rotators. The lcd-wb interface is supported on FIMC1. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boardsJonathan Bakker2-0/+12
The SHDCI controller on Aries devices is a little bit peculiar about the clocks and with a slightly off clock can run into errors such as: mmc2: ADMA error: 0x02000000 mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== mmc2: sdhci: Sys addr: 0x347e4cc4 | Version: 0x00002401 mmc2: sdhci: Blk size: 0x00007004 | Blk cnt: 0x0000fffc mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013 mmc2: sdhci: Present: 0x01fa0000 | Host ctl: 0x00000012 mmc2: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x0000010f mmc2: sdhci: Timeout: 0x0000000a | Int stat: 0x00000003 mmc2: sdhci: Int enab: 0x03ff004b | Sig enab: 0x03ff004b mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000001 mmc2: sdhci: Caps: 0x05e80080 | Caps_1: 0x00000000 mmc2: sdhci: Cmd: 0x0000163a | Max curr: 0x00000000 mmc2: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x00000000 mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc2: sdhci: Host ctl2: 0x00000000 mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x349a3208 mmc2: sdhci: ============================================ mmc2: sdhci: 349a3200: DMA 0x347e4cc0, LEN 0x0004, Attr=0x23 Specifically assign the MMC sclks to be parented from MPLL with specific rates that match the vendor kernel. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Enable ADC on Aries boardsJonathan Bakker1-1/+6
On Aries boards, the ADC is used for things such as jack detection and battery temperature monitoring. It is supplied by LDO4 of max8998, so only enable that regulator when we are actually using the ADC. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add an ADC nodeJonathan Bakker1-0/+12
The exynos-adc driver now supports the S5PV210, so add the DT node so that devices can use it. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boardsJonathan Bakker1-0/+9
The enable GPIO for the fixed vibrator regulator shouldn't be pulled in one direction or the other. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add si470x FM radio to Galaxy SPaweł Chmiel2-1/+48
Add support for the Silicon Labs si4709 FM radio, which can be found on Galaxy S GT-i9000 (but not on most of other Aries variants). Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boardsJonathan Bakker1-0/+69
The remaining i2c-gpio adapters that are common to all Aries boards have devices without mainline bindings attachted to them. Add them here for documentation. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add panel support to Aries boardsJonathan Bakker1-16/+52
Aries boards have an s6e63m0 AMOLED panel connected over i2c-spi. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add touchkey support to Aries boardsJonathan Bakker1-0/+58
Aries boards have soft touchkeys, manufactured by Cypress, attached over i2c-gpio. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add FSA9480 support to Aries boardsJonathan Bakker1-0/+36
The Fairchild FSA9480 is a USB mux connected over i2c-gpio. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add WM8994 support to Aries boardsJonathan Bakker2-2/+69
Aries boards have a Wolfson WM8994 sound card attached over gpio-i2c. There is currently no ASoC Machine Driver. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Disable pulls on GPIO I2C adapters for AriesJonathan Bakker1-0/+18
The bitbanged GPIO I2C adapters have external pull-ups attached so the internal pulls should be disabled for lower power usage. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Set keep-power-in-suspend for SDHCI1 on AriesJonathan Bakker1-0/+1
SDHCI1 is connected to a BCM4329 WiFi/BT chip which requires power to be kept over suspend. As the surrounding hardware supports this, mark it as such. This fixes WiFi after a suspend/resume cycle. Fixes: 170642468a51 ("ARM: dts: s5pv210: Add initial DTS for Samsung Aries based phones") Cc: <stable@vger.kernel.org> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Correct gpi pinctrl node nameJonathan Bakker1-1/+1
The node name was gpgi, but the pinctrl driver was registering the pins as just gpi and the "samsung,pins" i2s0 pinctrl entries refer to gpi. The public S5PC110 datasheet also refers to these pins as just gpi, so let's make sure everything is in sync and rename the node to gpi. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04bpf, arm: Optimize ALU ARSH K using asr immediate instructionLuke Nelson2-3/+10
This patch adds an optimization that uses the asr immediate instruction for BPF_ALU BPF_ARSH BPF_K, rather than loading the immediate to a temporary register. This is similar to existing code for handling BPF_ALU BPF_{LSH,RSH} BPF_K. This optimization saves two instructions and is more consistent with LSH and RSH. Example of the code generated for BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5) before the optimization: 2c: mov r8, #5 30: mov r9, #0 34: asr r0, r0, r8 and after optimization: 2c: asr r0, r0, #5 Tested on QEMU using lib/test_bpf and test_verifier. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20200501020210.32294-3-luke.r.nels@gmail.com
2020-05-04bpf, arm: Optimize ALU64 ARSH X using orrpl conditional instructionLuke Nelson1-2/+2
This patch optimizes the code generated by emit_a32_arsh_r64, which handles the BPF_ALU64 BPF_ARSH BPF_X instruction. The original code uses a conditional B followed by an unconditional ORR. The optimization saves one instruction by removing the B instruction and using a conditional ORR (with an inverted condition). Example of the code generated for BPF_ALU64_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1), before optimization: 34: rsb ip, r2, #32 38: subs r9, r2, #32 3c: lsr lr, r0, r2 40: orr lr, lr, r1, lsl ip 44: bmi 0x4c 48: orr lr, lr, r1, asr r9 4c: asr ip, r1, r2 50: mov r0, lr 54: mov r1, ip and after optimization: 34: rsb ip, r2, #32 38: subs r9, r2, #32 3c: lsr lr, r0, r2 40: orr lr, lr, r1, lsl ip 44: orrpl lr, lr, r1, asr r9 48: asr ip, r1, r2 4c: mov r0, lr 50: mov r1, ip Tested on QEMU using lib/test_bpf and test_verifier. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20200501020210.32294-2-luke.r.nels@gmail.com
2020-05-04ARM: dts: s5pv210: Add sleep GPIO configuration for Galaxy SJonathan Bakker1-0/+241
In order to minimize leakage current during sleep, set a config for sleep GPIOs. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add sleep GPIO configuration for Fascinate4GJonathan Bakker1-0/+243
In order to minimize leakage current during sleep, set a config for sleep GPIOs. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: dts: s5pv210: Add helper define for sleep gpio configJonathan Bakker1-0/+7
To simplify writing of sleep gpio configs, add a common helper similar to what is present for other Samsung CPUs. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-04ARM: multi_v7_defconfig: Enable r8a7742 SoCLad Prabhakar1-0/+1
Enable recently added r8a7742 (RZ/G1H) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588197415-13747-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-04ARM: shmobile: defconfig: Enable r8a7742 SoCLad Prabhakar1-0/+1
Enable recently added r8a7742 (RZ/G1H) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588197415-13747-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-04ARM: debug-ll: Add support for r8a7742Lad Prabhakar1-0/+10
Enable low-level debugging support for RZ/G1H (R8A7742). RZ/G1H uses SCIFA2 for the debug console. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588197415-13747-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-04ARM: dts: uniphier: add #address-cells and #size-cells to SPI nodesMasahiro Yamada5-0/+14
Documentation/devicetree/bindings/spi/spi-uniphier.txt requires #address-cells and #size-cells, but they are missing in actual DT files. Also, 'make ARCH=arm dtbs_check' is really noisy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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