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2020-02-21ARM: OMAP2+: Improve handling of ti-sysc related sysc_fieldsTony Lindgren1-7/+12
We can currently get a cryptic warning sysc_fields (ptrval) != (ptrval) if the legacy platform data has no sysc_fields defined while the newer dts data has them. This warning appears only when booting still with legacy "ti,hwmods" custom property set. This can happen at least with DSS related modules where we may not have sysc_fields defined in the in the legacy data. Let's not error out on missing legacy data sysc_fields, and show a more descriptive warning for other cases. Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-02-21ARM: 8959/1: Remove unused .fixup section in boot stubKees Cook1-1/+0
The boot stub does not emit a .fixup section at all anymore, so remove it. Link: https://lore.kernel.org/lkml/202002080058.FD1DDB1@keescook/ Suggested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-02-21ARM: 8961/2: Fix Kbuild issue caused by per-task stack protector GCC pluginArd Biesheuvel2-3/+5
When using plugins, GCC requires that the -fplugin= options precedes any of its plugin arguments appearing on the command line as well. This is usually not a concern, but as it turns out, this requirement is causing some issues with ARM's per-task stack protector plugin and Kbuild's implementation of $(cc-option). When the per-task stack protector plugin is enabled, and we tweak the implementation of cc-option not to pipe the stderr output of GCC to /dev/null, the following output is generated when GCC is executed in the context of cc-option: cc1: error: plugin arm_ssp_per_task_plugin should be specified before \ -fplugin-arg-arm_ssp_per_task_plugin-tso=1 in the command line cc1: error: plugin arm_ssp_per_task_plugin should be specified before \ -fplugin-arg-arm_ssp_per_task_plugin-offset=24 in the command line These errors will cause any option passed to cc-option to be treated as unsupported, which is obviously incorrect. The cause of this issue is the fact that the -fplugin= argument is added to GCC_PLUGINS_CFLAGS, whereas the arguments above are added to KBUILD_CFLAGS, and the contents of the former get filtered out of the latter before being passed to the GCC running the cc-option test, and so the -fplugin= option does not appear at all on the GCC command line. Adding the arguments to GCC_PLUGINS_CFLAGS instead of KBUILD_CFLAGS would be the correct approach here, if it weren't for the fact that we are using $(eval) to defer the moment that they are added until after asm-offsets.h is generated, which is after the point where the contents of GCC_PLUGINS_CFLAGS are added to KBUILD_CFLAGS. So instead, we have to add our plugin arguments to both. For similar reasons, we cannot append DISABLE_ARM_SSP_PER_TASK_PLUGIN to KBUILD_CFLAGS, as it will be passed to GCC when executing in the context of cc-option, whereas the other plugin arguments will have been filtered out, resulting in a similar error and false negative result as above. So add it to ccflags-y instead. Fixes: 189af4657186da08 ("ARM: smp: add support for per-task stack canaries") Reported-by: Merlijn Wajer <merlijn@wizzup.org> Tested-by: Tony Lindgren <tony@atomide.com> Acked-by: Kees Cook <keescook@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-02-21ARM: 8958/1: rename missed uaccess .fixup sectionKees Cook1-1/+1
When the uaccess .fixup section was renamed to .text.fixup, one case was missed. Under ld.bfd, the orphaned section was moved close to .text (since they share the "ax" bits), so things would work normally on uaccess faults. Under ld.lld, the orphaned section was placed outside the .text section, making it unreachable. Link: https://github.com/ClangBuiltLinux/linux/issues/282 Link: https://bugs.chromium.org/p/chromium/issues/detail?id=1020633#c44 Link: https://lore.kernel.org/r/nycvar.YSQ.7.76.1912032147340.17114@knanqh.ubzr Link: https://lore.kernel.org/lkml/202002071754.F5F073F1D@keescook/ Fixes: c4a84ae39b4a5 ("ARM: 8322/1: keep .text and .fixup regions closer together") Cc: stable@vger.kernel.org Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-02-21ARM: 8957/1: VDSO: Match ARMv8 timer in cntvct_functional()Florian Fainelli1-0/+2
It is possible for a system with an ARMv8 timer to run a 32-bit kernel. When this happens we will unconditionally have the vDSO code remove the __vdso_gettimeofday and __vdso_clock_gettime symbols because cntvct_functional() returns false since it does not match that compatibility string. Fixes: ecf99a439105 ("ARM: 8331/1: VDSO initialization, mapping, and synchronization") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-02-21ARM: allow unwinder to unwind recursive functionsRussell King1-1/+1
Allow the unwinder to unwind recursive functions if the stack makes progress, even if the PC is the same. This allows tracing through recursive __switchdev_handle_port_attr_set() and similar. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-02-20Merge branch 'omap-for-v5.6/fixes-rc2' into fixesTony Lindgren4-14/+10
2020-02-20ARM: exynos_defconfig: Enable SCHED_MC and ENERGY_MODELLukasz Luba1-0/+2
The Energy Model (EM) is needed to run Energy Aware Scheduler (EAS). Enable ENERGY_MODEL to make that happen. This will increase energy efficiency of the big.LITTLE platforms (e.g. Exynos5422) by smarter decisions in scheduling tasks in non-heavy workloads. Add SCHED_MC in order to create another level in scheduling domains: 'MC'. This improves scheduler's decisions on platforms with CPU clusters, such as big.LITTLE. Signed-off-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-02-20ARM: dts: exynos: Add dynamic-power-coefficient to Exynos5422 CPUsLukasz Luba1-0/+8
To use Energy Aware Scheduler (EAS) the Energy Model (EM) should be registered for CPUs. Add dynamic-power-coefficient into CPU nodes which let CPUFreq subsystem register the EM structures. This will increase energy efficiency of big.LITTLE platforms. The 'dynamic-power-coefficient' values have been obtained experimenting with different workloads. The power measurements taken from big CPU Cluster and LITTLE CPU Cluster has been compared with official documents and synthetic workloads estimations. The effective power ratio between Cortex-A7 and Cortex-A15 CPUs (~3x) is also aligned with documentation. Signed-off-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-02-20ARM: dts: dra7-l4: mark timer13-16 as pwm capableGrygorii Strashko1-0/+4
DMTimers 13 - 16 are PWM capable and also can be used for CPTS input signals generation. Hence, mark them as "ti,timer-pwm". Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-02-20ARM: dts: dra7xx-clocks: Fixup IPU1 mux clock parent sourceSuman Anna1-10/+2
The IPU1 functional clock is the output of a mux clock (represented by ipu1_gfclk_mux previously) and the clock source for this has been updated to be sourced from dpll_core_h22x2_ck in commit 39879c7d963e ("ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL"). ipu1_gfclk_mux is an obsolete clock now with the clkctrl conversion, and this clock source parenting is lost during the new clkctrl layout conversion. Remove this stale clock and fix up the clock source for this mux clock using the latest equivalent clkctrl clock. This restores the previous logic and ensures that the IPU1 continues to run at the same frequency of IPU2 and independent of the ABE DPLL. Fixes: b5f8ffbb6fad ("ARM: dts: dra7: convert to use new clkctrl layout") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-02-20ARM: dts: am437x-idk-evm: Fix incorrect OPP node namesSuman Anna1-2/+2
The commit 337c6c9a69af ("ARM: dts: am437x-idk-evm: Disable OPP50 for MPU") adjusts couple of OPP nodes defined in the common am4372.dtsi file, but used outdated node names. This results in these getting treated as new OPP nodes with missing properties. Fix this properly by using the correct node names as updated in commit b9cb2ba71848 ("ARM: dts: Use - instead of @ for DT OPP entries for TI SoCs"). Reported-by: Roger Quadros <rogerq@ti.com> Fixes: 337c6c9a69af ("ARM: dts: am437x-idk-evm: Disable OPP50 for MPU") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-02-20ARM: dts: dra7-evm: Rename evm_3v3 regulator to vsys_3v3Peter Ujfalusi1-2/+2
On the new schematics it is renamed and the same name is used on other dra7 boards. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-02-20ARM: dts: sun7i: Add LVDS panel support on A20Andrey Lebedev1-4/+21
Define pins for LVDS channels 0 and 1, configure reset line for tcon0 and provide sample LVDS panel, connected to tcon0. Signed-off-by: Andrey Lebedev <andrey@lebedev.lt> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-02-20ARM: dts: sunxi: Remove redundant assigned-clocksMaxime Ripard2-9/+0
The display DRC nodes have an assigned clocks property, while the driver also enforces it. Since assigned-clocks is pretty fragile anyway, let's just remove it. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-02-20ARM: dts: sunxi: Remove redundant assigned-clocksMaxime Ripard3-11/+0
The display backend nodes have an assigned clocks property, while the driver also enforces it. Since assigned-clocks is pretty fragile anyway, let's just remove it. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-02-20ARM: dts: droid4: Configure LED backlight for lm3532Tony Lindgren2-2/+12
With the LED backlight changes merged, we still need the dts configured to have backlight working for droid4. Based on an earlier patch from Pavel Machek <pavel@ucw.cz>, let's configure the backlight but update the value range to be more usable. We have a range of 256 register values split into 8 steps, so we can generate the brightness levels backwards with: $ for i in 0 1 2 3 4 5 6 7; do echo "255 - ${i} * (256 / 8)" | bc; done To avoid more confusion why the LCD backlight is still not on, let's also enable LED backlight as a loadable module for omap2plus_defconfig. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-02-19ARM: exynos_defconfig: Enable SquashFS and increase RAM block device sizeMarek Szyprowski1-1/+2
All modules built from exynos_defconfig occupy about 55M, so enable squashfs filesystem support and increase default ram block device size to 32M to enable deploying them on initrd. Such initrd, using squashfs requires at least 24M. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-02-18ARM: at91: pm: add quirk for sam9x60's ulp1Claudiu Beznea1-0/+4
On SAM9X60 2 nop operations has to be introduced after setting WAITMODE bit in CKGR_MOR. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-9-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: at91: pm: add plla disable/enable support for sam9x60Claudiu Beznea1-4/+113
Add PLLA enable/disable support for SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-8-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: at91: pm: s/sfr/sfrbu in pm_suspend.SClaudiu Beznea1-3/+3
s/sfr/sfrbu in pm_suspend.S. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-6-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: at91: pm: add pmc_version member to at91_pm_dataClaudiu Beznea4-0/+14
This will be used to differentiate b/w different PLLs settings to be applied in the final/first steps of the suspend/resume process by doing PLL specific configurations. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-5-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: at91: pm: add macros for plla disable/enableClaudiu Beznea1-27/+30
Add macros for PLLA disable and enable (in disable macro the PLLA state will also be saved). This prepares the field for PLLA disable/enable for suspend/resume on SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-4-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: at91: pm: revert do not disable/enable PLLA for ULP modesClaudiu Beznea1-0/+31
This reverts commit 2725d70aa5138284ba2cebf0ef51dd23e0c9ea21 ("ARM: at91: pm: do not disable/enable PLLA for ULP modes"). This is because PLLA is the clock source for CPU, PLLA should be disabled/enabled in the final/first phase of suspend/resume so that the power consumption in suspend/resume to be minimal and suspend/resume time to be minimized. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-3-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: at91: pm: use proper master clock register offsetClaudiu Beznea4-17/+46
SAM9X60's PMC has different master clock register offset than the other SoCs' PMC. Due to this, specify master clock register offset based on PMC compatible and pass it to pm_suspend.S since it is also needed in there. When PM part for SAM9X60 was published the SAM9X60's PMC (commit f6deae46039c ("clk: at91: add sam9x60 pmc driver")) wasn't integrated. Fixes: 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-2-git-send-email-claudiu.beznea@microchip.com
2020-02-18ARM: imx: Add missing of_node_put()Anson Huang5-2/+9
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx-udoo-neo: Use new pin names with DCE/DTE for UART pinsAnson Huang1-14/+14
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx-softing-vining-2000: Use new pin names with DCE/DTE for UART pinsAnson Huang1-4/+4
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx-sdb: Use new pin names with DCE/DTE for UART pinsAnson Huang1-6/+6
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx-sabreauto: Use new pin names with DCE/DTE for UART pinsAnson Huang1-2/+2
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx-nitrogen6sx: Use new pin names with DCE/DTE for UART pinsAnson Huang1-10/+10
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx: Add missing UART RTS/CTS pins muxAnson Huang1-0/+26
Some of UART RTS/CTS pins' DCE/DTE mux function are missing, add them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18ARM: dts: imx6sx: Improve UART pins macro definesAnson Huang1-86/+174
Add DCE/DTE to UART pins macro defines to distinguish the DCE and DTE functions, keep old defines at the end of file for some time to make it backward compatible. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17lib/vdso: Avoid highres update if clocksource is not VDSO capableThomas Gleixner1-7/+0
If the current clocksource is not VDSO capable there is no point in updating the high resolution parts of the VDSO data. Replace the architecture specific check with a check for a VDSO capable clocksource and skip the update if there is none. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124403.563379423@linutronix.de
2020-02-17lib/vdso: Cleanup clock mode storage leftoversThomas Gleixner1-1/+0
Now that all architectures are converted to use the generic storage the helpers and conditionals can be removed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124403.470699892@linutronix.de
2020-02-17ARM/arm64: vdso: Use common vdso clock mode storageThomas Gleixner5-28/+12
Convert ARM/ARM64 to the generic VDSO clock mode storage. This needs to happen in one go as they share the clocksource driver. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124403.363235229@linutronix.de
2020-02-17kvm: arm/arm64: Fold VHE entry/exit work into kvm_vcpu_run_vhe()Mark Rutland1-3/+0
With VHE, running a vCPU always requires the sequence: 1. kvm_arm_vhe_guest_enter(); 2. kvm_vcpu_run_vhe(); 3. kvm_arm_vhe_guest_exit() ... and as we invoke this from the shared arm/arm64 KVM code, 32-bit arm has to provide stubs for all three functions. To simplify the common code, and make it easier to make further modifications to the arm64-specific portions in the near future, let's fold kvm_arm_vhe_guest_enter() and kvm_arm_vhe_guest_exit() into kvm_vcpu_run_vhe(). The 32-bit stubs for kvm_arm_vhe_guest_enter() and kvm_arm_vhe_guest_exit() are removed, as they are no longer used. The 32-bit stub for kvm_vcpu_run_vhe() is left as-is. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200210114757.2889-1-mark.rutland@arm.com
2020-02-17ARM: vdso: Compile high resolution parts conditionallyThomas Gleixner1-0/+6
If the architected timer is disabled in the kernel configuration then let the core VDSO code drop the high resolution parts at compile time. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124402.622587341@linutronix.de
2020-02-17ARM: vdso: Remove unused functionThomas Gleixner1-7/+0
The function is nowhere used. Aside of that this check should only cover the high resolution parts of the VDSO which require a VDSO capable clocksource and not the complete functionality as the name suggests. Will be replaced with something more useful. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lkml.kernel.org/r/20200207124402.438179009@linutronix.de
2020-02-17ARM: shmobile: Replace <linux/clk-provider.h> by <linux/of_clk.h>Geert Uytterhoeven1-1/+1
The R-Car Gen2 platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200212100830.446-6-geert+renesas@glider.be
2020-02-17ARM: dts: mediatek: rename scpsys nodes to power-controllerMatthias Brugger3-3/+3
The nodes with name scpsys actually implement a power-controller. Rename the nodes to match the bindings description. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-17ARM: imx: Remove unused include of linux/of.h on mach-imx6sl.cAnson Huang1-1/+0
linux/of.h is NOT used on mach-imx6sl.c, remove it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: imx: Remove unused includes on mach-imx6q.cAnson Huang1-13/+0
Many includes are NOT used on mach-imx6q.c now, remove them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: imx: Remove unused include of linux/irqchip/arm-gic.hAnson Huang1-1/+1
linux/irqchip/arm-gic.h is NOT used at all, no need to include it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: dts: imx: make clks node name genericAnson Huang5-5/+5
Node name should be generic, use "clock-controller" instead of "ccm" for clks node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: dts: imx: make kpp node name genericAnson Huang5-5/+5
Node name should be generic, use "keypad" instead of "kpp" for kpp node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: dts: imx6qdl-gw553x: add lsm9ds1 iio imu/magn supportRobert Jones1-0/+31
Add one node for the accel/gyro i2c device and another for the separate magnetometer device in the lsm9ds1. Signed-off-by: Robert Jones <rjones@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: dts: imx: ventana: add fxos8700 on gateworks boardsRobert Jones3-0/+15
Add fxos8700 iio imu entries for Gateworks ventana SBCs. Signed-off-by: Robert Jones <rjones@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: dts: imx: make gpt node name genericAnson Huang5-9/+9
Node name should be generic, use "timer" instead of "gpt" for gpt node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17ARM: dts: imx: use generic name busPeng Fan18-35/+35
Per devicetree specification, generic names are recommended to be used, such as bus. i.MX AIPS is a AHB - IP bridge bus, so we could use bus as node name. Script: sed -i "s/\<aips@/bus@/" arch/arm/boot/dts/imx*.dtsi sed -i "s/\<aips@/bus@/" arch/arm/boot/dts/vf*.dtsi sed -i "s/\<aips-bus@/bus@/" arch/arm/boot/dts/imx*.dtsi sed -i "s/\<aips-bus@/bus@/" arch/arm/boot/dts/vf*.dtsi Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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