aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
AgeCommit message (Collapse)AuthorFilesLines
2019-08-02ARM: dts: stm32: add phy-dsi-supply property on stm32mp157c-ev1Yannick Fertré1-0/+1
The dsi physical layer is powered by the 1v8 power controller supply. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add audio codec support on stm32mp157a-dk1 boardOlivier Moysan1-0/+89
Add support of Cirrus cs42l51 audio codec on stm32mp157a-dk1 board. Configuration overview: - SAI2A is the CPU interface used for the codec audio playback - SAI2B is the CPU interface used for the codec audio record - SAI2A is configured as a clock provider for the audio codec - SAI2A&B are configured as slave of the audio codec - SAI2A&B share the same interface of the audio codec Note: In master mode, cs42l51 audio codec provides a bitclock at 64 x FS, regardless of data width. This means that slot width is always 32 bits. Set slot width to 32 bits and slot number to 2 in SAI2A&B endpoint nodes, to match this constraint. dai-tdm-slot-num and dai-tdm-slot-width properties are used here, assuming that i2s is a special case of tdm, where slot number is 2. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add syscfg to ADC on stm32mp157cFabrice Gasnier1-0/+1
On stm32mp157c, the ADC inputs are multiplexed with analog switches which have reduced performances when their supply is below 2.7V (vdda by default). Add syscfg registers that can be used on stm32mp157c, to get full ADC analog performances. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add pwm cells to stm32f746Fabrice Gasnier1-0/+12
STM32 Timers support generic 3 cells PWM to encode PWM number, period and polarity. Fixes: 9bd7b77af8e4 ("ARM: dts: stm32: add Timers driver for stm32f746 MCU") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add pwm cells to stm32f429Fabrice Gasnier1-0/+12
STM32 Timers support generic 3 cells PWM to encode PWM number, period and polarity. Fixes: c0e14fc712d9 ("ARM: dts: stm32: add Timers driver for stm32f429 MCU") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add pwm cells to stm32mp157cFabrice Gasnier1-0/+12
STM32 Timers support generic 3 cells PWM to encode PWM number, period and polarity. Fixes: 61fc211c484d ("ARM: dts: stm32: add timers support to stm32mp157c") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: fix -Wall W=1 compilation in stm32mp157 pinctrl for mcanErwan Le Ray1-1/+1
Fix compilations warnings detected by -Wall W=1 compilation option: - node has a unit name, but no reg property Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add booster for ADC analog switches on stm32mp157cFabrice Gasnier1-0/+6
Booster for ADC analog input switches can be used when Vdda is below 2.7V to get maximum ADC analog performances. Add booster for ADC analog switches on stm32mp157c. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: enable m4 coprocessor support on STM32MP157a-dk1Fabien Dessenne1-0/+10
Enable m4 coprocessor for STM32MP157a-dk1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: declare copro reserved memories on STM32MP157a-dk1Fabien Dessenne1-0/+36
Declare reserved memories shared by the processors for STM32MP157a-dk1 Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: enable m4 coprocessor support on STM32MP157c-ed1Fabien Dessenne1-0/+10
Enable m4 coprocessor for STM32MP157c-ed1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: declare copro reserved memories on STM32MP157c-ed1Fabien Dessenne1-0/+36
Declare reserved memories shared by the processors for STM32MP157c-ed1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add m4 remoteproc support on STM32MP157cFabien Dessenne1-0/+20
Declare the M4 remote processor in a sub-node of the mlahb simple bus. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add missing vdda-supply to adc on stm32h743i-evalFabrice Gasnier1-0/+1
Add missing vdda-supply required by STM32 ADC. Fixes: 090992a9ca54 ("ARM: dts: stm32: enable ADC on stm32h743i-eval board") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: add missing vdda-supply to adc on stm32429i-evalFabrice Gasnier1-0/+7
Add missing vdda-supply required by STM32 ADC. Fixes: 7465d81191a1 ("ARM: dts: stm32: enable ADC on stm32f429i-eval board") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: stm32: remove fixed regulator unit address on stm32429i-evalFabrice Gasnier1-12/+6
vref fixed regulator shouldn't have unit address and reg properties. Rename the label and phandle to "vref" according to the schematics. Also remove it from simple-bus. Fixes: 7465d81191a1 ("ARM: dts: stm32: enable ADC on stm32f429i-eval board") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-08-02ARM: dts: aspeed: tiogapass: Add Riser cardVijay Khemka1-0/+230
Added i2c mux for riser card and multiple ava card and its sensor components for Facebook tiogapass platform Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-08-02ARM: dts: aspeed: tiogapass: Move battery sensorVijay Khemka1-5/+1
Moved adc7 hwmon battery sensor to correct label to be read by single applications for all adc sensors. Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-08-02asm-generic: Remove redundant arch-specific rules for simd.hHerbert Xu1-1/+0
Now that simd.h is in include/asm-generic/Kbuild we don't need the arch-specific Kbuild rules for them. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 82cb54856874 ("asm-generic: make simd.h a mandatory...") Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2019-08-02ARM: dts: aspeed: Add Facebook Wedge100 BMCTao Ren2-0/+150
Add initial version of device tree for Facebook Wedge100 AST2400 BMC platform. Signed-off-by: Tao Ren <taoren@fb.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-08-02ARM: dts: aspeed: Add Facebook Wedge40 BMCTao Ren2-0/+142
Add initial version of device tree for Facebook Wedge40 AST2400 BMC platform. Signed-off-by: Tao Ren <taoren@fb.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-31ARM: vexpress: Cleanup cppcheck shifting warningPhong Tran1-2/+2
Fix below warning from cppcheck tool using BIT() macro: "Shifting signed 32-bit value by 31 bits is undefined behaviour errors" Signed-off-by: Phong Tran <tranmanphong@gmail.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-07-31ARM: dts: vexpress: Add missing newline at end of fileGeert Uytterhoeven1-1/+1
"git diff" says: \ No newline at end of file after modifying the file. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-07-31ARM: dts: vexpress: add missing SPDX GPL-2.0 license identifierSudeep Holla1-0/+1
Commit b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") seem to have missed this one file. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-07-31ARM: dts: aspeed: swift: Fix FSI GPIOsMatt Spinler1-2/+2
Change the FSI clock and data GPIOs to match what the hardware turned out to use. Fixes: 8e8fd0cbd7c5 ("ARM: dts: aspeed: Add Swift BMC machine") Signed-off-by: Matt Spinler <spinler@us.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Adriana Kobylak <anoo@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-30ARM: dts: socfpga: add missing reset-names for dmaDinh Nguyen1-0/+1
The dma dts node was missing the reset-names = "dma". The reset driver needs this line to get the reset property. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGAMarek Vasut1-2/+6
Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew to minimum (-420 ps), to improve signal integrity. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: Fix up button mapping on VINING FPGAMarek Vasut1-5/+17
Add missing buttons and signals to the VINING FPGA device tree, so they are presented to the userspace via gpio-keys evdev. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: update to new Denali NAND bindingMasahiro Yamada3-9/+15
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add reset properties for DMADinh Nguyen1-0/+2
Add both the reset and reset-ocp properties for the DMA node on Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add the QSPI OCP reset property on arria10Dinh Nguyen1-1/+2
The QSPI module needs the OCP reset bit deasserted as well. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: exynos: Use standard arrays of generic PHYs for EHCI/OHCI devicesMarek Szyprowski8-79/+22
Move USB PHYs to a standard arrays for Exynos EHCI/OHCI devices. This resolves the conflict between Exynos EHCI/OHCI sub-nodes and generic USB device bindings. Once the Exynos EHCI/OHCI sub-nodes are removed, the boards can finally provide sub-nodes for the USB devices using generic USB device bindings. Suggested-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20190726081453.9456-4-m.szyprowski@samsung.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-07-27ARM: dts: rockchip: Cleanup style around assignment operatorKrzysztof Kozlowski4-9/+9
Use a space before and after assignment operator to have consistent style. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-27crypto: ghash - add comment and improve help textEric Biggers1-1/+1
To help avoid confusion, add a comment to ghash-generic.c which explains the convention that the kernel's implementation of GHASH uses. Also update the Kconfig help text and module descriptions to call GHASH a "hash function" rather than a "message digest", since the latter normally means a real cryptographic hash function, which GHASH is not. Cc: Pascal Van Leeuwen <pvanleeuwen@verimatrix.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Pascal Van Leeuwen <pvanleeuwen@verimatrix.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26ARM: dts: gemini: Mount root from mtdblock3Linus Walleij2-2/+2
The third mtdblock device named "Application" is where we want to mount our root filesystem. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-26ARM: dts: gemini: Switch to redboot partition parsingLinus Walleij2-62/+8
This switches the kernel to parse the Redboot partitions in the SL93512r and the NAS4220B properly using the right compatible string instead of using hard-coded partitions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-26ARM: dts: gemini: Fix up confused pin settingsLinus Walleij1-8/+11
The SL93512r board has its pin muxing set up for the wrong ASIC: SL3516 instead of SL3512 that it is using. Fix it up and reference the right GPIO for the WPS button. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-26crypto: arm/aes-scalar - unexport en/decryption routinesArd Biesheuvel1-3/+0
The scalar table based AES routines are not used by other drivers, so let's keep it that way and unexport the symbols. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/aes-cipher - switch to shared AES inverse SboxArd Biesheuvel1-39/+1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/ghash - provide a synchronous versionArd Biesheuvel1-26/+52
GHASH is used by the GCM mode, which is often used in contexts where only synchronous ciphers are permitted. So provide a synchronous version of GHASH based on the existing code. This requires a non-SIMD fallback to deal with invocations occurring from a context where SIMD instructions may not be used. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/aes-neonbs - provide a synchronous version of ctr(aes)Ard Biesheuvel1-0/+65
AES in CTR mode is used by modes such as GCM and CCM, which are often used in contexts where only synchronous ciphers are permitted. So provide a synchronous version of ctr(aes) based on the existing code. This requires a non-SIMD fallback to deal with invocations occurring from a context where SIMD instructions may not be used. We have a helper for this now in the AES library, so wire that up. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/aes-ce - provide a synchronous version of ctr(aes)Ard Biesheuvel1-0/+43
AES in CTR mode is used by modes such as GCM and CCM, which are often used in contexts where only synchronous ciphers are permitted. So provide a synchronous version of ctr(aes) based on the existing code. This requires a non-SIMD fallback to deal with invocations occurring from a context where SIMD instructions may not be used. We have a helper for this now in the AES library, so wire that up. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/aes - use native endiannes for key scheduleArd Biesheuvel2-16/+13
Align ARM's hw instruction based AES implementation with other versions that keep the key schedule in native endianness. This will allow us to merge the various implementations going forward. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/aes-neonbs - switch to library version of key expansion routineArd Biesheuvel2-3/+3
Switch to the new AES library that also provides an implementation of the AES key expansion routine. This removes the dependency on the generic AES cipher, allowing it to be omitted entirely in the future. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: aes - rename local routines to prevent future clashesArd Biesheuvel1-4/+4
Rename some local AES encrypt/decrypt routines so they don't clash with the names we are about to introduce for the routines exposed by the generic AES library. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-26crypto: arm/aes-ce - cosmetic/whitespace cleanupArd Biesheuvel1-60/+56
Rearrange the aes_algs[] array for legibility. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-25ARM: dts: rockchip: add veyron-tiger boardMatthias Kaehlcke2-0/+126
Also known as the AOpen Chromebase Mini. tiger and fievel are share the same board, tiger has a display and touchscreen, fievel not. Use the fievel .dts as base and add the extra bits. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25ARM: dts: rockchip: add veyron-fievel boardMatthias Kaehlcke2-0/+299
Also known as AOpen Chromebox Mini. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25ARM: dts: rockchip: consolidate veyron panel and backlight settingsMatthias Kaehlcke6-224/+67
veyron jaq, jerry, minnie and speedy have mostly redundant regulator and pinctrl configurations for the panel/backlight. Consolidate these pieces in the eDP .dtsi. Also change the default power supply for the panel to 'panel_regulator', instead of overriding it in all the board files. pinky is the only device that uses 'vcc33_lcd' (the prior default), so overwrite it in this case. pinky doesn't have a complete display configuration, to keep things as they were delete the common nodes that didn't exist previously in pinky's board file. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25ARM: dts: rockchip: move rk3288-veryon display settings into a separate fileMatthias Kaehlcke2-114/+125
The chromebook .dtsi file contains common settings for veyron Chromebooks with eDP displays. Some veyron devices with a display aren't Chromebooks (e.g. 'tiger' aka 'AOpen Chromebase Mini'), move display related bits from the chromebook .dtsi into a separate file to avoid redundant DT settings. The new file is included from the chromebook .dtsi and can be included by non-Chromebook devices with a display. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.