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2019-07-25ARM: dts: rockchip: Limit WiFi TX power on rk3288-veyron-jerryMatthias Kaehlcke1-0/+149
The downstream Chrome OS 3.14 kernel for jerry limits WiFi TX power through calibration data in the device tree [1]. Add a DT node for the WiFi chip and use the downstream calibration data. Not all calibration data entries have the length specified in the binding (Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt), however this is the data used by the downstream ('official') kernel and the binding mentions that "the length can vary between hw versions". [1] https://crrev.com/c/271237 Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25ARM: dts: stm32: enable FMC2 NAND controller on stm32mp157c-ev1Christophe Kerello1-0/+16
This patch enables FMC2 NAND controller used on stm32mp157c-ev1. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-07-25ARM: dts: stm32: add FMC2 NAND controller pins muxing on stm32mp157c-ev1Christophe Kerello1-0/+44
This patch adds FMC2 NAND controller pins muxing used on stm32mp157c-ev1. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-07-25ARM: dts: stm32: add FMC2 NAND controller support on stm32mp157cChristophe Kerello1-0/+19
This patch adds FMC2 NAND controller support used by stm32mp157c SOC. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-07-25ARM: dts: stm32: activate dma for qspi on stm32mp157Ludovic Barre1-0/+3
This patch activates dma for qspi on stm32mp157. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-07-24ARM: bcm283x: Reduce register ranges for UART, SPI and I2CStefan Wahren1-3/+3
The assigned register ranges for UART, SPI and I2C were too wasteful. In order to avoid overlapping with the new functions on BCM2711 reduce the ranges. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Acked-by: Eric Anholt <eric@anholt.net>
2019-07-24arm: use swiotlb for bounce buffering on LPAE configsChristoph Hellwig4-1/+74
The DMA API requires that 32-bit DMA masks are always supported, but on arm LPAE configs they do not currently work when memory is present above 4GB. Wire up the swiotlb code like for all other architectures to provide the bounce buffering in that case. Fixes: 21e07dba9fb11 ("scsi: reduce use of block bounce buffers"). Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-07-24ARM: dts: sunxi: Prefer A31 bindings for IRClément Péron1-1/+1
Since A31, memory mapping of the IR driver has changed. Prefer the A31 bindings instead of A13. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Sean Young <sean@mess.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-24ARM: dts: sunxi: Prefer A31 bindings for IRClément Péron3-3/+3
Since A31, memory mapping of the IR driver has changed. Prefer the A31 bindings instead of A13. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Sean Young <sean@mess.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-24ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7Tony Lindgren3-2/+10
We are currently using a wrong register for dcan revision. Although this is currently only used for detecting the dcan module, let's fix it to avoid confusion. Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-07-24ARM: dts: Fix flags for gpio7Tony Lindgren3-3/+3
The ti,no-idle-on-init and ti,no-reset-on-init flags need to be at the interconnect target module level for the modules that have it defined. Otherwise we get the following warnings: dts flag should be at module level for ti,no-idle-on-init dts flag should be at module level for ti,no-reset-on-init Reviewed-by: Suman Anna <s-anna@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-07-24ARM: OMAP2+: Fix missing SYSC_HAS_RESET_STATUS for dra7 epwmssTony Lindgren1-1/+2
TRM says PWMSS_SYSCONFIG bit for SOFTRESET changes to zero when reset is completed. Let's configure it as otherwise we get warnings on boot when we check the data against dts provided data. Eventually the legacy platform data will be just dropped, but let's fix the warning first. Reviewed-by: Suman Anna <s-anna@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-07-23ARM: defconfig: enable cpufreq driver for RPiNicolas Saenz Julienne2-0/+11
This enables on both multi_v7_defconfig and bcm2835_defconfig the new firmware based clock and cpufreq drivers for the Raspberry Pi platform. In the case of bcm2835_defconfig, as the cpufreq subsystem was disabled, the conservative governor was selected as default since it better handles the high frequency transition latency. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
2019-07-23Merge tag 'imx-fixes-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixesOlof Johansson6-7/+7
i.MX fixes for 5.3: - Fix i.MX8MM SAI3 RXC/TXFS pinmux configuration. - Fix i.MX7ULP usb-phy unit address to drop extra '0x' notation. - Fix typo of clock frequency property name in a few i.MX6UL board I2C buses. - Drop "fsl,imx6sx-sai" from i.MX8M SAI device, as it's not compatible with i.MX6SX SAI. * tag 'imx-fixes-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mq: fix SAI compatible arm64: dts: imx8mm: Correct SAI3 RXC/TXFS pin's mux option #1 ARM: dts: imx6ul: fix clock frequency property name of I2C buses ARM: dts: imx7ulp: Fix usb-phy unit address format Link: https://lore.kernel.org/r/20190723090827.GU15632@dragon Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-23ARM: defconfig: u8500: Add new driversLinus Walleij1-1/+11
This enables the new or updates driver options for U8500 that got merged into v5.3-rc1: - CMA, MCDE driver, LIMA driver and the Samsung S6D16D0 driver enabled by default bringing up the new graphics support. Include the LOGO so we can see when the graphics are live. - We use the IIO hwmon bridge for reflecting temperature in the system. - Set MUSB to PIO mode as this is the one working most stable for the time being. - HWSPINLOCK needs to be set to get the hardware semaphore driver to compile and link properly. Link: https://lore.kernel.org/r/20190723081523.13079-2-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-23ARM: defconfig: u8500: Refresh defconfigLinus Walleij1-14/+8
This refreshes the outdated U8500 defconfig: some options moved around, PS/2 mouse is no longer default on, crypto options moved around etc. Link: https://lore.kernel.org/r/20190723081523.13079-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-23ARM: dts: bcm: bcm47094: add missing #cells for mdio-bus-muxArnd Bergmann1-0/+3
The mdio-bus-mux has no #address-cells/#size-cells property, which causes a few dtc warnings: arch/arm/boot/dts/bcm47094-linksys-panamera.dts:129.4-18: Warning (reg_format): /mdio-bus-mux/mdio@200:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #address-cells value arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #size-cells value Add the normal cell numbers. Link: https://lore.kernel.org/r/20190722145618.1155492-1-arnd@arndb.de Fixes: 2bebdfcdcd0f ("ARM: dts: BCM5301X: Add support for Linksys EA9500") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-23ARM: davinci: fix sleep.S build error on ARMv4Arnd Bergmann1-0/+1
When building a multiplatform kernel that includes armv4 support, the default target CPU does not support the blx instruction, which leads to a build failure: arch/arm/mach-davinci/sleep.S: Assembler messages: arch/arm/mach-davinci/sleep.S:56: Error: selected processor does not support `blx ip' in ARM mode Add a .arch statement in the sources to make this file build. Link: https://lore.kernel.org/r/20190722145211.1154785-1-arnd@arndb.de Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-07-23ARM: dts: sunxi: Fix the HDMI PHY nameMaxime Ripard3-3/+3
Even though the binding mentions that the PHY name must be "phy", it turns out that all our DTs had "hdmi-phy" instead. The code doesn't care about the phy-names property, so we can just change our DTs to match the binding, without any side effect. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-23ARM: dts: sunxi: Remove simple-panel compatibleMaxime Ripard2-2/+2
simple-panel based bindings need only the display compatible, and simple-panel isn't documented anywhere. Remove it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-23ARM: ux500: simplify and move debug UARTLinus Walleij1-7/+2
The debug UART code defined three different virtual addresses while only one is ever used. Get rid of this, and move the UART remapping to 0xfffe8000 where DTCM reside on some platforms but not on Ux500, so it can be reused moving the UART out of the vmalloc area. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: dts: imx6sll: move GIC to right location in DTAnson Huang1-9/+9
GIC is inside of SoC from architecture perspective, it should be located inside of soc node in DT. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: move GIC to right location in DTAnson Huang1-12/+12
GIC is inside of SoC from architecture perspective, it should be located inside of soc node in DT. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6sl: move GIC to right location in DTAnson Huang1-9/+9
GIC is inside of SoC from architecture perspective, it should be located inside of soc node in DT. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6sx: move GIC to right location in DTAnson Huang1-9/+9
GIC is inside of SoC from architecture perspective, it should be located inside of soc node in DT. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: vf610-zii-scu4-aib: Drop unused pinctrl_i2c3 pinmux configAndrey Smirnov1-7/+0
Pinctrl_i2c3 pinmux config is not used anywhere. Drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: vf610-zii-scu4-aib: Fix pinctrl_i2c1's identationAndrey Smirnov1-1/+2
Fix pinctrl_i2c1's inconsistent identation. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: vf610-zii-spb4: Drop unused pinctrl_i2c1 pinmux configAndrey Smirnov1-7/+0
Pinctrl_i2c1 pinmux config is not used anywhere. Drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: ux500: set pull-up on STUIB STMPE IRQ lineLinus Walleij1-0/+11
Set up the STMPE IRQ line to be in pull-up mode. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: dts: ux500: Fix up the thermal nodesLinus Walleij2-30/+21
The thermal driver for the DB8500 was never properly converted to device tree, the node should definitely be activated for all board variants so move this down into the main SoC DTSI, and default on. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: dts: ste: Update coresight DT bindingsLeo Yan1-2/+2
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel and static replicator, so can dismiss warning during initialisation. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Lee Jones <lee.jones@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: ux500: Stop populating the PRCMU devices earlyLinus Walleij1-1/+0
The PRCMU devices are getting populated from the MFD driver and that is enough for them to come up. We already have an early quirk for the things that need to happen really early and the PRCMU timer that need to be registered really early will find its own node just fine as the timer/clocksource subsystem looks through the whole device tree for compatible nodes. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-23ARM: dts: imx6ull: Add support for PHYTEC phyBOARD-Segin with i.MX 6ULLStefan Riedmueller7-0/+315
In addition to the PHYTEC phyCORE-i.MX 6UL the PHYTEC phyBOARD-Segin is also available with the PHYTEC phyCORE-i.MX 6ULL. So this adds support for this SOM and its baseboards. It comes in a full featured option with either NAND flash or eMMC and in a low cost option only available with NAND flash. The hardware specs are: - Full featured with NAND or eMMC: * i.MX 6ULL Y2 * 512MB DDR3 memory * 512MB NAND flash or 4GB/8GB eMMC * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers - Low cost with NAND: * i.MX 6ULL Y0 * 256MB DDR3 memory * 128MB NAND flash * Single 10/100 Ethernet * USB OTG * RS232 * MicroSD external storage * I2C * Further I/O options via Expansion headers Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Move machine include to dts filesStefan Riedmueller2-1/+1
Move the imx6ul.dtsi include to the dts files so it is easier to reuse the SOM dtsi for e.g. an i.MX 6ULL SOM. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Move ECSPI interface to board include fileStefan Riedmueller2-14/+16
The ECSPI interface is available on the expansion connector of every PHYTEC phyBOARD-Segin. Move its definition to the board include file for better reuse. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: phycore: Add eMMC at usdhc2Stefan Riedmueller1-0/+24
The phyCORE-i.MX 6UL/ULL now can have eMMC instead of the NAND flash memory. Add the eMMC node and disable it by default so it can be enabled in case it is populated. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Only enable NAND if it is populatedStefan Riedmueller2-1/+5
The phyCORE-i.MX 6UL/ULL now comes either with NAND flash or eMMC. We have to configure the populated memory type in the device tree files. So the GPMI node gets disabled by default and only enabled if populated. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Make FEC and ethphy configurable in dtsStefan Riedmueller3-5/+19
To disable Ethernet interfaces in case they are not populated make the FEC and Ethernet PHY status configurable in the dts files. Also change the Ethernet PHYs labels to make them correspond to the MDIO address. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Fix LED naming for phyCORE and PEB-EVAL-01Stefan Riedmueller2-9/+10
Fix node name for the user LEDs to prevent the pinctrl of the phyCORE's leds node from being overwritten. Also use more generic names for user LEDs. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Reduce eth drive strengthStefan Riedmueller2-10/+10
Reduce the drive strength for the MDC, MDIO and TX pins of FEC1 and FEC2 on the phyBOARD-Segin to improve signal quality and EMC. Also disable internal pull-ups on the MDC and MDIO pins. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: segin: Add boot media to dts filenameStefan Riedmueller2-3/+4
There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash available. The dts filename needs to reflect that to differentiate both. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name schemeStefan Riedmueller5-7/+7
Use the same name scheme for the phyBOARD-Segin and the phyCORE-i.MX 6UL as is used for the PHYTEC phyBOARD-Mira and phyCORE-i.MX 6. This is only a cosmetic change and there is no functional change intended. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-23ARM: configs: aspeed: Refresh defconfigsJoel Stanley2-67/+40
A noop change to git rid of cruft. Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-23ARM: configs: aspeed: Enable commonly used network functionalityWilliam A. Kennington III2-0/+16
This addresses some assumptions made by systemd about having multiple routing table support in the kernel. systemd-networkd will try and provision mutliple routing tables + policies and will silently break neighbor advertisement responses due to policy configurations on a single table. It also adds support for SLAAC based router settings and faster duplicate address detection. Signed-off-by: William A. Kennington III <wak@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-23ARM: dts: aspeed: Add SGPM pinmuxHongwei Zhang1-0/+5
Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-23ARM: dts: aspeed: tiogapass: Add VR devicesVijay Khemka1-0/+36
Adds voltage regulators Infineon pxe1610 devices to Facebook tiogapass platform. Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-23ARM: dts: aspeed: Add Lenovo Hr855xg2 BMCAndrew Peng2-0/+664
Initial introduction of Lenovo Hr855xg2 family equipped with Aspeed 2500 BMC SoC. Hr855xg2 is a x86 server development kit with a ASPEED ast2500 BMC manufactured by Lenovo. This adds the Hr855xg2 platform device tree file used by the Hr855xg2 BMC machines. Signed-off-by: Andrew Peng <pengms1@lenovo.com> Signed-off-by: Yonghui Liu <liuyh21@lenovo.com> Signed-off-by: Lisa Liu <liuyj19@lenovo.com> Signed-off-by: Harry Sung <hsung1@lenovo.com> Signed-off-by: Derek Lin <dlin23@lenovo.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-23ARM: dts: aspeed: Add Facebook Minipack BMCTao Ren2-0/+430
Add initial version of device tree for Facebook Minipack ast2500 BMC. Signed-off-by: Tao Ren <taoren@fb.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-07-22arm: Use common cpu_topology structure and functions.Atish Patra2-74/+6
Currently, ARM32 and ARM64 uses different data structures to represent their cpu topologies. Since, we are moving the ARM64 topology to common code to be used by other architectures, we can reuse that for ARM32 as well. Take this opprtunity to remove the redundant functions from ARM32 and reuse the common code instead. To: Russell King <linux@armlinux.org.uk> Signed-off-by: Atish Patra <atish.patra@wdc.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> (on TC2) Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-07-22ARM: dts: sunxi: Unify the DE2 bus clocks orderMaxime Ripard4-16/+16
The DE2 bus takes two clocks, named bus and mod according to the binding. However, the order of these clocks change from one SoC to another. Even though it might not be an issue in most cases, having consistency will help if we ever need to have some code to deal with deprecated bindings, and in general it's just better. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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