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2019-04-12ARM: dts: iwg23s-sbc: Enable HS-USBBiju Das1-0/+4
Enable HS-USB device for the iWave SBC based on RZ/G1C. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add HSUSB device nodesBiju Das1-0/+35
Define the r8a77470 generic part of the HSUSB0/1 device nodes. Currently the renesas_usbhs driver doesn't handle multiple phys and we don't have a proper hardware to validate such driver changes. So for hsusb1 it is assumed that usbphy0 will be enabled by either channel0 host or device. In future, if any boards support hsusb1, we will need to add multiple phy support in the renesas_usbhs driver and override the board dts to enable the same. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: iwg23s-sbc: Enable USB USB2.0 HostBiju Das1-0/+8
Enable USB2.0 host on the iwg23s sbc. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) deviceBiju Das1-0/+50
Define the r8a77470 generic part of the USB2.0 Host Controller device nodes (ehci[01]/ohci[01]). Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: iwg23s-sbc: Enable USB Phy[01]Biju Das1-0/+32
Enable USB phy[01] on iWave iwg23s sbc based on RZ/G1C SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add USB PHY DT supportBiju Das1-0/+56
Define the r8a77470 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: shmobile: Enable USB [EO]HCI HCD PLATFORM support in shmobile_defconfigBiju Das1-0/+2
The USB [EO]HCI controller on RZ/G1C SoC doesn't have PCI bridge like other R-Car Gen2 devices. So enable generic USB [EO]HCI HCD PLATFORM support in shmobile_defconfig. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: shmobile: Enable PHY_RCAR_GEN3_USB2 in shmobile_defconfigBiju Das1-0/+1
Enable PHY_RCAR_GEN3_USB2 in shmobile_defconfig so that boards based on RZ/G1C SoC design can use the corresponding driver. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add VIN supportCao Van Dong1-0/+22
Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add PWM supportCao Van Dong1-0/+70
Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add HSCIF supportCao Van Dong1-0/+48
Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogsDouglas Anderson2-0/+8
Even though upstream Linux doesn't yet go into deep enough suspend to get DDR into self refresh, there is no harm in setting these pins up. They'll only actually do something if we go into a deeper suspend but leaving them configed always is fine. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12ARM: rockchip: Mark pm-init functions __initDouglas Anderson1-2/+2
The functions rk3288_config_bootdata() and rk3288_suspend_init() are only called in the context of rockchip_suspend_init() which is already marked __init. We can mark them __init too. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288Matthias Kaehlcke1-0/+4
The value was determined with the following method: - take CPUs 1-3 offline - for each OPP - set cpufreq min and max freq to OPP freq - start dhrystone benchmark - measure CPU power consumption during 10s - calculate Cx for OPPx - Cx = (Px - P1) / (Vx²fx - V1²f1) [1] using the following units: mW / Ghz / V [2] - C = avg(C2, ..., Cn) [1] see commit 4daa001a1773 ("arm64: dts: juno: Add cpu dynamic-power-coefficient information") [2] https://patchwork.kernel.org/patch/10493615/#22158551 FTR, these are the values for the different OPPs: freq (kHz) mV Px (mW) Cx 126000 900 39 216000 900 66 370 312000 900 95 372 408000 900 122 363 600000 900 177 359 696000 950 230 363 816000 1000 297 361 1008000 1050 404 362 1200000 1100 528 362 1416000 1200 770 377 1512000 1300 984 385 1608000 1350 1156 394 Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11ARM: dts: rockchip: bulk convert gpios to their constant counterpartsHeiko Stuebner40-827/+827
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11ARM: dts: rockchip: Add BT_EN to the power sequence for veyronMatthias Kaehlcke1-3/+10
Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the Bluetooth/WiFi module. On devices with a Broadcom module the signal needs to be asserted to use Bluetooth. Note that BT_ENABLE_L is a misnomer in the schematics, the signal actually is active-high. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyronMatthias Kaehlcke1-4/+0
Some veyron devices have a Bluetooth controller connected on UART0. The UART needs to operate at a high speed, however setting the clock rate at initialization has no practical effect. During initialization user space adjusts the UART baudrate multiple times, which ends up changing the SCLK rate. After a successful initiatalization the clk is running at the desired speed (48MHz). Remove the unnecessary clock rate configuration from the DT. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11ARM: dts: stm32: enable cec on stm32mp157a-dk1 boardYannick Fertré1-0/+7
Enable CEC (Consumer Electronics Control) device. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add cec pins muxing on stm32mp157Yannick Fertré1-0/+21
Add a new pin muxing for cec. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add ltdc pins muxing on stm32mp157Yannick Fertré1-0/+138
Add ltdc pins muxing on stm32mp157. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add I2C sleep pins muxing on stm32mp157Yannick Fertré1-0/+29
Add I2C sleep pins muxing for low power mode. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add power supply of otm8009a on stm32mp157c-dk2Yannick Fertré1-0/+1
This patch adds a new property (power-supply) to panel otm8009a (orisetech) on stm32mp157c-dk2 & regulator v3v3. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Enable STM32F769 clock driverGabriel Fernandez1-0/+4
This patch enables clocks for STM32F769 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add stpmic1 support on stm32mp157a dk1 boardPascal Paillet1-8/+150
This patch adds stpmic1 support on stm32mp157a dk1 board. The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. The DMAs are disabled because the PMIC generates a very few traffic and DMA channels may lack for other usage. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add stpmic1 support on stm32mp157c ed1 boardPascal Paillet1-16/+140
This patch adds stpmic1 support on stm32mp157c ed1 board. The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. The DMAs are disabled because the PMIC generates a very few traffic and DMA channels may lack for other usage. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add spdfirx pins to stm32mp157cOlivier Moysan1-0/+13
This patch adds spdifrx support on stm32mp157c eval board. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add spdifrx support on stm32mp157cOlivier Moysan1-0/+13
This patch adds support of STM32 SPDIFRX on stm32mp157c. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Add romem and temperature calibration on stm32f429Fabrice Gasnier1-0/+13
Add & enable stm32 factory-programmed memory. Describe temperature sensor calibration cells. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Add romem and temperature calibration on stm32mp157cFabrice Gasnier1-0/+13
Add & enable stm32 factory-programmed memory. Describe temperature sensor calibration cells. Non-volatile calibration data is made available by stm32mp157c bootrom in bsec_dataX registers. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Add clock on stm32mp157c syscfgFabrice Gasnier1-0/+1
STM32 syscfg needs a clock to access registers. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: enable IPCC mailbox support on STM32MP157a-dk1Fabien Dessenne1-0/+4
Enable STM32 IPCC mailbox driver for STM32MP157a-dk1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: enable IPCC mailbox support on STM32MP157c-ed1Fabien Dessenne1-0/+4
Enable STM32 IPCC mailbox driver for STM32MP157c-ed1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add IPCC mailbox support on STM32MP157cFabien Dessenne1-0/+15
Add configuration on DT for IPCC mailbox driver. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32mp157a dk1 boardLudovic Barre1-0/+20
This patch adds sdmmc1 support on stm32mp157a dk1 board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32mp157c ed1 boardLudovic Barre2-0/+105
This patch adds sdmmc1 support on stm32mp157c ed1 board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32mp157cLudovic Barre1-0/+14
This patch adds support of sdmmc1 on stm32mp157c. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32h743i disco boardLudovic Barre1-0/+20
This patch adds sdmmc1 support on stm32h743i disco board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32h743i eval boardLudovic Barre2-1/+90
This patch adds sdmmc1 support on stm32h743i eval board. This board has an external driver to control signal direction polarity. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32h743Ludovic Barre1-0/+14
This patch adds support of sdmmc1 on stm32h743. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: imx6dl-sabreauto: update opp table for auto partAnson Huang1-0/+15
Update i.MX6DL automotive part's opp table according to i.MX6DL automotive datasheet Rev.9, 11/2018, it adds 996MHz set-point support as below: LDO enabled(min value): 996MHz: VDDARM: 1.275V, VDDSOC: 1.175V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.125V, VDDSOC: 1.150V; Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, as the max value of LDO output can NOT exceed 1.3V, so 25mV is NOT added for VDDARM. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx: Use generic node names for Zii dtsFabio Estevam6-26/+26
The devicetree specification recommends using generic node names. Some Zii dts files already follow such recommendation, but some don't, so use generic node names for consistency among the Zii dts files. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx: Switch Zii dts to SPDX identifierFabio Estevam6-228/+6
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx6q-logicpd: Reduce inrush current on USBH1Adam Ford1-0/+1
Some USB peripherals draw more power, and the sourcing regulator take a little time to turn on. This patch fixes an issue where some devices occasionally do not get detected, because the power isn't quite ready when communication starts, so we add a bit of a delay. Fixes: 1c207f911fe9 ("ARM: dts: imx: Add support for Logic PD i.MX6QD EVM") Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx6q-logicpd: Reduce inrush current on startAdam Ford1-0/+1
The main 3.3V regulator sources a series of additional regulators. This patch adds a small delay, so when the 3.3V regulator comes on it delays a bit before the subsequent regulators can come on. This reduces the inrush current a bit on the external DC power supply to help prevent a situation where the sourcing power supply cannot source enough current and overloads and the kit fails to start. Fixes: 1c207f911fe9 ("ARM: dts: imx: Add support for Logic PD i.MX6QD EVM") Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx6q-logicpd: Shutdown LCD regulator during suspendAdam Ford1-2/+2
The LCD power sequencer is very finicky. The backlight cannot be driven until after the sequencer is done. Until now, the regulators were marked with 'regulator-always-on' to make sure it came up before the backlight. This patch allows the LCD regulators to power down and prevent the backlight from being used again until the sequencer is ready. This reduces standby power consumption by ~100mW. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx6q-logicpd: Enable Analog audio captureAdam Ford1-2/+2
The original submission had functional audio out and was based on reviewing other boards using the same wm8962 codec. However, the Logic PD board uses an analog microphone which was being disabled for a digital mic. This patch corrects that and explicitly sets the gpio-cfg pins all to 0x0000 which allows the analog microphone to capture audio. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx6sll: add cooling-cells for cpu-freq cooling deviceAnson Huang1-0/+1
Add #cooling-cells for i.MX6SLL cpu-freq cooling device usage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx50: Add Kobo Aura DTSJonathan Neuschäfer2-1/+260
The Kobo Aura is an e-book reader released in 2013. With the devicetree in its current state, the kernel will boot and run for about ten seconds. To solve this, the embedded controller needs to be told that the system should stay powered on. This will be done in a later patchset. - The IOMUXC mode bits for the SD interfaces were taken from the vendor's U-Boot fork. - The bus width of the eMMC is 4 bits in the vendor kernel, but I achieved better performance with 8 bits. - The SDIO clock frequency for the WiFi chip is 25MHz in the vendor kernel, but the WiFi chip (BCM43362) supports 50MHz, which works reliably on this board and gives slightly better performance. - The I2C pins' IOMUXC settings come from the vendor's U-Boot fork. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx: Fix the AR803X phy-modeFabio Estevam13-13/+13
Commit 6d4cd041f0af ("net: phy: at803x: disable delay only for RGMII mode") exposed an issue on imx DTS files using AR8031/AR8035 PHYs. The end result is that the boards can no longer obtain an IP address via UDHCP, for example. Quoting Andrew Lunn: "The problem here is, all the DTs were broken since day 0. However, because the PHY driver was also broken, nobody noticed and it worked. Now that the PHY driver has been fixed, all the bugs in the DTs now become an issue" To fix this problem, the phy-mode property needs to be "rgmii-id", which has the following meaning as per Documentation/devicetree/bindings/net/ethernet.txt: "RGMII with internal RX and TX delays provided by the PHY, the MAC should not add the RX or TX delays in this case)" Tested on imx6-sabresd, imx6sx-sdb and imx7d-pico boards with successfully restored networking. Based on the initial submission from Steve Twiss for the imx6qdl-sabresd. Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Soeren Moch <smoch@web.de> Tested-by: Steve Twiss <stwiss.opensource@diasemi.com> Tested-by: Adam Thomson <Adam.Thomson@diasemi.com> Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com> Tested-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11ARM: dts: imx6qdl-var-dart: Use new CODEC reset pin nameAndrew F. Davis1-1/+1
The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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