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2011-03-09microblaze: Do not use "la" pseudo instruction - use addik insteadMichal Simek1-6/+6
"la" pseudo instruction is only translation to "addik". Use directly "addik" which is described in the MB reference guide. Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-03-09microblaze: Optimize BE/LE bootup detectingMichal Simek1-5/+7
Save 0x1 word to rodata section and remove online value loading if DTB is passed from bootloader. It saves two asm instructions in bootup. Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-02-07microblaze: Fix msr instruction detectionMichal Simek1-8/+7
Fix msr instructions detection. The current code just use msrclr for loading msr content and compare it with proper MSR content. If msrclr is not implemented r8 contains pc address. Previous code wanted to use MSR carry bit but if msrclr wasn't implemented carry wasn't cleared. Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-01-28microblaze: Fix DTB passing from bootloaderMichal Simek1-2/+12
Little endian system needs to check OF_DT_HEADER but it is swapped because it is in big-endian. Microblaze LE provides lwr instruction which loads magic number in BIG endian format which can be compared. There is used the fact that if you write 0x1 as word and load it as byte then you get for big-endian zero and 1 for little-endian. Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-08-04microblaze: Allow PAGE_SIZE configurationSteven J. Magnani1-2/+2
Allow developer to configure memory page size at compile time. Larger pages can improve performance on some workloads. Based on PowerPC code. Signed-off-by: Steven J. Magnani <steve@digidescorp.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-05-06microblaze: Quiet section mismatch warningsSteven J. Magnani1-1/+2
_start is located in .text, which causes mismatch warnings with machine_early_init() and start_kernel() in .init.text. Signed-off-by: Steven J. Magnani <steve@digidescorp.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-01microblaze: head.S typo fixMichal Simek1-2/+2
I forget to change register name in comments. Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-01microblaze: Use MICROBLAZE_TLB_SIZE in asm codeMichal Simek1-1/+1
TLB size was hardcoded in asm code. This patch brings ability to change TLB size only in one place. (mmu.h). Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-04-01microblaze: Support systems without lmb bramMichal Simek1-0/+6
When the system has no lmb bram, main memory should be start from zero because of microblaze vectors. DTS fragment could look like: DDR2_SDRAM: memory@0 { device_type = "memory"; reg = < 0x0 0x10000000 >; } ; Then you have to setup CONFIG_KERNEL_BASE_ADDR=0 which caused that kernel physical start address will be zero. On reset vector place will be jump to 0x100 and on 0x100 starts kernel text. You have to solve how to load the kernel before cpu starts. Tested with XMD. Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-03-11microblaze: Change temp register for cmdlineMichal Simek1-6/+7
For copy was used r7 register when CONFIG_CMDLINE_BOOL option is enabled. But r7 stores pointer to fdt that's why machine_early_init not detect compiled-in DTB. I also moved kernel PID setup to have TLB init in one block Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-10-15of: add common header for flattened device tree representationGrant Likely1-1/+1
Add a common header file for working with the flattened device tree data structure and merge the shared data tags used by Microblaze and PowerPC Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au>
2009-09-21microblaze: Improve checking mechanism for MSR instructionMichal Simek1-8/+5
It is more safe to use clear instead of msrset. We save some instructions too. Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-09-21microblaze: Add checking mechanism for MSR instructionMichal Simek1-2/+15
It was necessary to use fourth parameter(r8) in early_printk to show messages on console. Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-07-27microblaze: Clear print messages for DTB passing via r7Michal Simek1-0/+3
It is necessary to zeroed r7 when r7 points to bad dtb - this caused that we have correct messages about compiled-in dtb or passing via r7 Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-07-27microblaze: Not to clear r7 after copying DTB to kernelMichal Simek1-1/+0
I can't clear r7 because if I do it I lose information where DTB come from. Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-07-27microblaze: Final support for statically linked DTBJohn Williams1-4/+11
If r7 is zero at kernel boot, or does not point to a valid DTB, then we fall back to a DTB (assumed to be) linked statically in the kernel, instead of blindly copying bogus cruft into the kernel DTB memory region Signed-off-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-05-26microblaze_mmu_v2: MMU update for startup codeMichal Simek1-0/+190
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-03-27microblaze_v8: assembler files head.S, entry-nommu.S, syscall_table.SMichal Simek1-0/+56
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
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