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2016-05-28MIPS: hazards.h: Fix typoAndrea Gelmini1-4/+4
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: chenhc@lemote.com Cc: james.hogan@imgtec.com Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13317/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENTHuacai Chen1-3/+4
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21MIPS: hazards: Add hazard macros for tlb readJames Hogan1-0/+52
Add hazard macros to <asm/hazards.h> for the following hazards around tlbr (TLB read) instructions, which are used in TLB dumping code and some KVM TLB management code: - mtc0_tlbr_hazard Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in all cases on the assumption that tlbr always has similar data user timings to tlbw. - tlb_read_hazard Between tlbr and mfc0 (various TLB registers). This is copied from tlbw_use_hazard in all cases on the assumption that tlbr has similar data writer characteristics to tlbw, and mfc0 has similar data user characteristics to loads and stores. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10078/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-17MIPS: asm: hazards: Add MIPSR6 definitionsMarkos Chandras1-4/+5
Add the MIPSR6 related definitions to MIPS hazards Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-04-11MIPS: Get rid of the use of .macro in C code.Ralf Baechle1-128/+243
It fails with LTO and probably has always been a fragile. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-21Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-nextRalf Baechle1-1/+1
2013-02-17MIPS: Netlogic: No hazards needed for XLR/XLSJayachandran C1-1/+1
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4788/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-3/+3
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-25/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPSKevin Cernekee1-1/+2
Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel images will compile and run. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Clean up whitespace warning in hazards.hKevin Cernekee1-2/+2
Use a tab on second and subsequent lines of multiline #if's, for consistency with the next commit. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: Alchemy: remove SOC_AU1X00 in favor of MIPS_ALCHEMYManuel Lauss1-2/+2
Remove the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-14MIPS: Loongson 2 needs no hazard barriers.Zhang Le1-2/+3
Quoting from Loongson2FUserGuide.pdf: 5.22.1 Hazards The processor detects most of the pipeline hazards in hardware, including CP0 hazards and load hazards. No NOP instructions are required to correct instruction sequences. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30MIPS: Alchemy: MIPS hazard workarounds are not required.Manuel Lauss1-2/+2
The Alchemy manuals state: "All pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute correctly. Therefore, it is not necessary to pad legacy MIPS hazards (such as load delay slots and coprocessor accesses) with NOPs." Run-tested on Au12x0, without any ill effects. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-11MIPS: NEC VR5500 processor support fixupShinya Kuribayashi1-1/+2
Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.David Daney1-2/+2
For Cavium CPU, we treat the same as R10000, in that all hazards are dealt with in hardware. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle1-0/+271
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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