linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2012-12-13	MIPS: PMC-Sierra Yosemite: Remove support.	Ralf Baechle	1	-25/+0
	Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07	MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS	Kevin Cernekee	1	-1/+2
	Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel images will compile and run. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07	MIPS: Clean up whitespace warning in hazards.h	Kevin Cernekee	1	-2/+2
	Use a tab on second and subsequent lines of multiline #if's, for consistency with the next commit. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05	MIPS: Alchemy: remove SOC_AU1X00 in favor of MIPS_ALCHEMY	Manuel Lauss	1	-2/+2
	Remove the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-14	MIPS: Loongson 2 needs no hazard barriers.	Zhang Le	1	-2/+3
	Quoting from Loongson2FUserGuide.pdf: 5.22.1 Hazards The processor detects most of the pipeline hazards in hardware, including CP0 hazards and load hazards. No NOP instructions are required to correct instruction sequences. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30	MIPS: Alchemy: MIPS hazard workarounds are not required.	Manuel Lauss	1	-2/+2
	The Alchemy manuals state: "All pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute correctly. Therefore, it is not necessary to pad legacy MIPS hazards (such as load delay slots and coprocessor accesses) with NOPs." Run-tested on Au12x0, without any ill effects. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-11	MIPS: NEC VR5500 processor support fixup	Shinya Kuribayashi	1	-1/+2
	Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11	MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.	David Daney	1	-2/+2
	For Cavium CPU, we treat the same as R10000, in that all hazards are dealt with in hardware. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11	MIPS: Move headfiles to new location below arch/mips/include	Ralf Baechle	1	-0/+271
	Signed-off-by: Ralf Baechle <ralf@linux-mips.org>