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2007-10-29[MIPS] SMTC: Allow control over TC assignment to vpe0.Kevin D. Kissell1-13/+44
Modify the SMTC initialization code to allow boot-time specification not only of how many VPEs and TCs to use, but also how many TCs out of the allowed pool are to be bound to VPE 0. The new boot option is "vpe0tcs=N", where N is an integer. Using it in combination with the existing options allows arbitrary assignments across the 2 VPEs of a 34K. e.g. "maxtcs=3 vpe0tcs=1" forces VPE0 to have 1 TC, while VPE1 has 2, and "maxtcs=4 vpe0tcs=3" forces VPE0 to have 3 TCs, while VPE1 gets 1. If no vpe0tcs option is specified, the traditional algorithm of evenly dividing TCs between available VPEs, with the odd "slop" going to VPE0, is retained. The reason for doing this is to allow a finer balancing of TCs which can handle I/O interrupts on Malta (those on VPE 0) and those which cannot. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Kill num_online_cpus() loops.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle1-3/+3
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Dyntick support for SMTC:Ralf Baechle1-35/+32
The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] IRQ Affinity Support for SMTC on Malta PlatformKevin D. Kissell1-0/+63
Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-24[MIPS] SMTC: Make ack_bad_irq() safe with no IM backstop.Ralf Baechle1-1/+4
Issue reported and original patch by Kevin Kissel, cleaner (imho) implementation by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] SMTC: Move MIPS_CPU_IPI_IRQ definition into header.Ralf Baechle1-2/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] SMTC: Fix modpost warning.Ralf Baechle1-1/+1
WARNING: vmlinux.o(.text+0xcf54): Section mismatch: reference to .init.text:smp_bootstrap (between 'smtc_boot_secondary' and 'ipi_interrupt') Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] MT: Enable coexistence of AP/SP with VSMP and SMTC.Ralf Baechle1-16/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] SMTC: smtc_timer_broadcast ignores its arguments, make it void.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] SMTC: Declare static what should be static.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] SMTC: Statically initialize irq_ipi[].Ralf Baechle1-6/+6
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] SMTC: Use current_cpu_data instead of cpu_data[smp_processor_id]Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-26[MIPS] Count timer interrupts correctly.Chris Dearman1-1/+1
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-20[MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle1-3/+3
For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-11[MIPS] SMTC: Fix warning.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-09wrap access to thread_infoRoman Zippel1-1/+1
Recently a few direct accesses to the thread_info in the task structure snuck back, so this wraps them with the appropriate wrapper. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-03-29[MIPS] SMTC: Fix recursion in instant IPI replay code.Ralf Baechle1-7/+33
local_irq_restore -> raw_local_irq_restore -> irq_restore_epilog -> smtc_ipi_replay -> smtc_ipi_dq -> spin_unlock_irqrestore -> _spin_unlock_irqrestore -> local_irq_restore The recursion does abort when there is no more IPI queued for a CPU, so this isn't usually fatal which is why we got away with this for so long until this was discovered by code inspection. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-03-29[MIPS] SMTC: Fix false trigger of debug code on single VPE.Ralf Baechle1-5/+15
Make smtc_setup_irq() update the list of interrupts which need to be watched by the debug code itself. Also there is no need to initialize the IPI swint when running with a single VPE, so don't initialize it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-03-29[MIPS] SMTC: irq_{enter,leave} and kstats keeping for relayed timer ints.Ralf Baechle1-0/+5
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-26[MIPS] Make SMTC_IDLE_HOOK_DEBUG a proper option in Kconfig.debug.Ralf Baechle1-11/+8
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] SMTC: Make a bunch of functions and variables static.Ralf Baechle1-9/+9
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] Whitespace cleanups.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] SMTC: remove unused atomic_postclearRalf Baechle1-22/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto1-11/+1
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-24[MIPS] SMTC: Fix module build by exporting symbolRalf Baechle1-0/+3
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-24[MIPS] SMTC: Fix TLB sizing bug for TLB of 64 >= entriesRalf Baechle1-2/+5
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-23[MIPS] SMTC: Instant IPI replay.Ralf Baechle1-21/+33
SMTC pseudo-interrupts between TCs are deferred and queued if the target TC is interrupt-inhibited (IXMT). In the first SMTC prototypes, these queued IPIs were serviced on return to user mode, or on entry into the kernel idle loop. The INSTANT_REPLAY option dispatches them as part of local_irq_restore() processing, which adds runtime overhead (hence the option to turn it off), but ensures that IPIs are handled promptly even under heavy I/O interrupt load. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-19[MIPS] SMTC: Fix cp0 hazard.Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto1-0/+1
Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-01[MIPS] SMTC: Synchronize cp0 counters on bootup.Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-08[MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle1-13/+13
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Replace board_timer_setup function pointer by plat_timer_setup.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-07-13[MIPS] SMTC: Reformat to Linux style.Ralf Baechle1-29/+29
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-02[PATCH] irq-flags: MIPS: Use the new IRQF_ constantsThomas Gleixner1-1/+1
Use the new IRQF_ constants and remove the SA_INTERRUPT define Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-27[PATCH] spin/rwlock init cleanupsIngo Molnar1-2/+2
locking init cleanups: - convert " = SPIN_LOCK_UNLOCKED" to spin_lock_init() or DEFINE_SPINLOCK() - convert rwlocks in a similar manner this patch was generated automatically. Motivation: - cleanliness - lockdep needs control of lock initialization, which the open-coded variants do not give - it's also useful for -rt and for lock debugging in general Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19[MIPS] MT: Improved multithreading support.Ralf Baechle1-0/+1322
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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