aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mm/c-r4k.c (follow)
AgeCommit message (Collapse)AuthorFilesLines
2007-10-16[MIPS] Cache: Provide more information on cache policy on bootup.Ralf Baechle1-3/+7
This should help making bug reports for the gadzillion of cores with all their configuration and synthesis options more useful. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle1-4/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle1-6/+6
This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Avoid indexed cacheops.Ralf Baechle1-46/+28
On MP configurations it's highly dubious what this code will actually affect since blasting away cachelines may or may not do the right thing wrt. cache coherency. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle1-4/+18
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] Replace use of stext with _stext.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang1-0/+54
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30[MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.Ralf Baechle1-3/+7
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30[MIPS] Remove redundant r4k_blast_icache() callsAtsushi Nemoto1-8/+4
r4k_flush_cache_all() and r4k_flush_cache_mm() case: these are noop if the CPU did not have dc_aliases. It would mean we do not need to care about icache here. r4k_flush_cache_range case: if r4k_flush_cache_mm() did not need to care about icache, it would be same for this function. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-01[MIPS] Remove __flush_icache_pageAtsushi Nemoto1-77/+0
__flash_icache_page is unused, so kill it. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27[MIPS] c-r4k: Convert init functions from inline to __init.Ralf Baechle1-10/+10
With more recent compilers inline doesn't necessarily means a function will always be inlined. So leave that decission to the compiler and make the function as __init. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27[MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.Atsushi Nemoto1-2/+2
c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged I-caches, but this does not work for flushing other task's icache. This is for example triggered by copy_to_user_page() called from ptrace(2). Use indexed flush for such cases. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27[MIPS] Retire flush_icache_page from mm use.Ralf Baechle1-1/+1
On the 34K the redundant cache operations were causing excessive stalls resulting in realtime code running on the second VPE missing its deadline. For all other platforms this patch is just a significant performance improvment as illustrated by below benchmark numbers. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 25Kf 2.6.18-rc4 533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K 25Kf 2.6.18-rc4-p 533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K 4Kc 2.6.18-rc4 80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K 4Kc 2.6.18-rc4-p 80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K 34Kc 2.6.18-rc4 40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K 34Kc 2.6.18-rc4-p 40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K BCM1480 2.6.18-rc4 700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K BCM1480 2.6.18-rc4-p 700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385 TX49-16K 2.6.18-rc3 197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K TX49-16K 2.6.18-rc3-p 197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K TX49-32K 2.6.18-rc3 396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K TX49-32K 2.6.18-rc3-p 396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K Original patch by me with enhancements by Atsushi Nemoto. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
2006-09-27[MIPS] c-r4k: Typo fix.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] vr41xx: Replace magic number for P4K bit with symbol.Yoichi Yuasa1-1/+1
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] vr41xx: Changed workaround to recommended methodYoichi Yuasa1-4/+3
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.Yoichi Yuasa1-1/+3
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle1-4/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel1-1/+0
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-29[MIPS] 74K: Assume it will also have an AR bit in config7Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29[MIPS] Treat CPUs with AR bit as physically indexed.Ralf Baechle1-3/+8
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29[MIPS] Fix handling of 0 length I & D caches.Chris Dearman1-23/+41
Don't ask. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29[MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman1-5/+18
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-06[MIPS] Save write-only Config.OD from being clobberedSergei Shtylyov1-0/+34
Save the Config.OD bit from being clobbered by coherency_setup(). This bit, when set, fixes various errata in the early steppings of Au1x00 SOCs. Unfortunately, the bit was write-only on the most early of them. In addition, also restore the bit after a wakeup from sleep. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Treat R14000 like R10000.Kumba1-0/+4
Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Fix deadlock on MP with cache aliases.Ralf Baechle1-9/+30
A proper fix would involve introducing the notion of shared caches but at this stage of 2.6.17 that's going to be too intrusive and not needed for current hardware; aside I think some discussion will be needed. So for now on the affected SMP configurations which happen to suffer from cache aliases we make use of the fact that a single cache will be shared by all processors. This solves the deadlock issue and will improve performance by getting rid of the smp_call_function overhead. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Add missing 34K processor IDsNigel Stephens1-0/+1
The 34K is very much like a 24K on steroids. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19[MIPS] Use __ffs() instead of ffs() for waybit calculation.Atsushi Nemoto1-8/+8
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19[MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19[MIPS] Fix tx49_blast_icache32_page_indexed.Atsushi Nemoto1-1/+2
Fix the cache index value in tx49_blast_icache32_page_indexed(). This is a damage by de62893bc0725f8b5f0445250577cd7a10b2d8f8 commit. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21[MIPS] TX49XX has prefetch.Atsushi Nemoto1-0/+1
The TX49XX has the prefetch instruction. It supports only Pref_Load (hint 0). Actually changes in this patch except for Kconfig are not have any effects, I added these changes to prevent misuse of unsupported hints. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto1-4/+9
If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-28[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle1-5/+11
When a CPU has no scache, the scache flushing functions currently aren't getting initialized and the NULL pointer is eventually called as a function. Initialize the scache flushing functions as a noop when there's no scache. Initial patch by me and most of the debugging done by Martin Michlmayr. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto1-90/+14
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common use. They are built by __BUILD_BLAST_CACHE_RANGE(). Use protected_cache_op() macro for various protected_ routines. Output code should be logically same. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07[MIPS] Remove wrong __user tags.Atsushi Nemoto1-4/+3
This fixes sparse warnings 'dereference of noderef expression'. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle1-2/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle1-16/+17
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer1-0/+1
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Minor code cleanup.Thiemo Seufer1-15/+15
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29More .set push/pop.Thiemo Seufer1-2/+2
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer1-2/+2
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle1-3/+2
will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle1-2/+1
a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Mark a few variables __read_mostly.Ralf Baechle1-1/+7
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Better interface to run uncached cache setup code.Thiemo Seufer1-4/+2
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Sparseify MIPS.Ralf Baechle1-3/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Base Au1200 2.6 support.Pete Popov1-0/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Use intermediate variable.Thiemo Seufer1-3/+3
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.