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2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-8/+8
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-09-13MIPS: uasm: Add INS and EXT instructions.Steven J. Hill1-5/+18
These are MIPS32R2 instructions for merging and extracting bit fields from one GPR into another. Signed-off-by: Steven J. Hill <sjhill@mips.com>
2012-07-23MIPS: Fixup ordering of micro assembler instructions.Steven J. Hill1-32/+30
A number of new instructions have been added to the micro assembler causing the list to no longer be in alphabetical order. This patch fixes up the name ordering. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-01-18MIPS: Use WARN() in uasm for better diagnostics.David Daney1-24/+16
On the off chance that uasm ever warns about overflow, there is no way to know what the offending instruction is. Change the printks to WARNs, so we can get a nice stack trace. It has the added benefit of being much more noticeable than the short single line warning message, so is less likely to be ignored. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1905/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-01-18MIPS: Add LDX and LWX instructions to uasm.David Daney1-1/+6
Needed by Octeon II optimized TLB handlers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Pachwork: https://patchwork.linux-mips.org/patch/1903/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-01-18MIPS: Add DINSM to uasm.David Daney1-1/+10
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1875/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Apply CN63XXP1 errata workarounds.David Daney1-1/+19
The CN63XXP1 needs a couple of workarounds to ensure memory is not written in unexpected ways. All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We pass a flag to the assembler to cover compiler generated code, and patch uasm for the dynamically generated code. The write buffer threshold is reduced to 4. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: uasm: Add option to export uasm API.David Daney1-49/+82
A 'select EXPORT_UASM' in Kconfig will cause the uasm to be exported for use in modules. When it is exported, all the uasm data and code cease to be __init and __initdata. Also daddiu_bug cannot be __cpuinitdata if uasm is exported. The cleanest thing is to just make it normal data. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: uasm: Add BBIT0 and BBIT1 instructionsDavid Daney1-1/+21
These are OCTEON specific instructions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: uasm: Add drotr32 and uasm_i_drotr_safe.David Daney1-5/+8
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1495/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-04-12MIPS: uasm: Add OR instruction.Ralf Baechle1-1/+3
This is needed for the fix of the M3 workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-04-12MIPS: Add SYSCALL to uasm.David Daney1-2/+17
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/976/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Add TLBR and ROTR to uasm.David Daney1-2/+7
The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.hFlorian Fainelli1-2/+1
Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-17MIPS: Add drotr and dins instructions to uasm.David Daney1-3/+13
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15[MIPS] Make two functions staticDmitri Vorobiev1-2/+2
The following routines uasm_rel_highest() uasm_rel_higher() are needlessly defined global. This patch makes them static. Compile-tested using a customized config for the Malta board. Booting the same board up to the shell prompt was also successful with this patch applied. Spotted by sparse. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Reimplement clear_page/copy_pageThiemo Seufer1-7/+19
Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle1-34/+34
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-02-01[MIPS] Split the micro-assembler from tlbex.c.Thiemo Seufer1-0/+576
This patch moves the micro-assembler in a separate implementation, as it is useful for further run-time optimizations. The only change in behaviour is cutting down printk noise at kernel startup time. Checkpatch complains about macro parameters which aren't protected by parentheses. I believe this is a flaw in checkpatch, the paste operator used in those macros won't work with parenthesised parameters. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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