linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2015-06-02	powerpc/e500mc: Remove dead L2 flushing code in idle_e500.S	Scott Wood	1	-9/+0
	This code can never be executed as it is only built when CONFIG_PPC_E500MC is unset, but the only CPUs that have CPU_FTR_L2CSR require CONFIG_PPC_E500MC and do not have the MSR/HID0-based nap mechanism that this file uses. Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-07-11	powerpc: Use CURRENT_THREAD_INFO instead of open coded assembly	Stuart Yoder	1	-2/+2
	Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-10-11	powerpc: e500mc: Fix: use CONFIG_PPC_E500MC in idle_e500.S	Bharat Bhushan	1	-1/+1
	It is wrongly using undefined CONFIG_E500MC. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-06-27	powerpc/e500mc: Add support for the wait instruction in e500_idle	Scott Wood	1	-0/+12
	e500mc cannot doze or nap due to an erratum (as well as having a different mechanism than previous e500), but it has a "wait" instruction that is similar to doze. On 64-bit, due to the soft-irq-disable mechanism, the existing book3e_idle should be used instead. Signed-off-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-03	powerpc: Fix for getting CPU number in power_save_ppc32_restore()	Kumar Gala	1	-1/+2
	The calculation to get TI_CPU based off of SPRG3 was just plain wrong, meaning that we were getting garbage for the CPU number on 6xx/G3/G4 based SMP boxes in this code. Just offset off the stack pointer (to get to thread_info) like all the other references to TI_CPU do. This was pointed out by Chen Gong <G.Chen@freescale.com> [paulus@samba.org - use rlwinm r12,r11,... instead of rlwinm r12,r1,...; tophys()] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-26	powerpc/e500mc: flush L2 on NAP for e500mc	Kumar Gala	1	-0/+9
	If we have an L2CSR register (e500mc) we need to flush the L2 before going to nap. We use the HW flush mechanism provided in that register. The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by any code in the kernel. Additionally we didn't reuse the exist L2CR feature bit as this is intended for the 7xxx L2CR register and L2CSR is part of the new Freescale "Book-E" registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-26	powerpc/85xx: add DOZE/NAP support for e500 core	Kumar Gala	1	-0/+84
	The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>