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2007-02-08[POWERPC] Use ARRAY_SIZE macro when appropriateAhmed S. Darwish3-7/+7
Use ARRAY_SIZE macro already defined in linux/kernel.h Signed-off-by: Ahmed S. Darwish <darwish.07@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-08[POWERPC] Fix ppc64's writing to struct file_operationsStephen Rothwell1-4/+7
In preparation for marking file_operations as const. Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-08[POWERPC] ppc: use syslog macro for the printk log levelRobert P. J. Day1-1/+2
Use the appropriate logging macro for the priority level for that printk call. Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-08[POWERPC] ppc: cs4218_tdm remove extra braceMariusz Kozlowski1-1/+0
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-08[POWERPC] Add mpc52xx/lite5200 PCI supportGrant Likely5-1/+437
Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-08[POWERPC] Only use H_BULK_REMOVE if the firmware supports itPaul Mackerras3-8/+16
The previous patch changing pSeries to use H_BULK_REMOVE broke the JS20 blade, where the firmware doesn't support H_BULK_REMOVE. This adds a firmware check so that on machines that don't have H_BULK_REMOVE, we just use the H_REMOVE call as before. Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07[POWERPC] Fixup error handling when emulating a floating point instructionKumar Gala1-22/+60
When we do full FP emulation its possible that we need to post a SIGFPE based on the results of the emulation. The previous code ignored this case completely. Additionally, the Soft_emulate_8xx case had two issues. One, we should never generate a SIGFPE since the code only does data movement. Second, we were interpreting the return codes incorrectly, it returns 0 on success, 1 on illop and -EFAULT on a data access error. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-02-07[POWERPC] Enable interrupts if we are doing fp math emulationKumar Gala1-14/+15
Anytime we are emulating an instruction we are going to be doing some form of get_user() to get the instruction image to decode. Since get_user() might sleep we need to ensure we have interrupts enabled or we might see something like: Debug: sleeping function called from invalid context at arch/powerpc/kernel/traps.c:697 in_atomic():0, irqs_disabled():1 Call Trace: [D6023EB0] [C0007F84] show_stack+0x58/0x174 (unreliable) [D6023EE0] [C0022C34] __might_sleep+0xbc/0xd0 [D6023EF0] [C000D158] program_check_exception+0x1d8/0x4fc [D6023F40] [C000E744] ret_from_except_full+0x0/0x4c --- Exception: 700 at 0x102a7100 LR = 0xdb9ef04 However, we want to ensure that interrupts are disabled when handling a trap exception that might be used for a kernel breakpoint. This is why ProgramCheck is marked as EXC_XFER_STD instead of EXC_XFER_EE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-02-06[POWERPC] Added kprobes support to ppc32Kumar Gala5-5/+15
Added kprobes to ppc32 platforms that have use single_step_exception. This excludes 4xx and anything Book-E since their debug mechanisms for single stepping are completely different. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-02-07[POWERPC] Make pSeries use the H_BULK_REMOVE hypervisor callPaul Mackerras2-5/+47
H_BULK_REMOVE lets us remove 4 entries from the MMU hash table with one hypervisor call. This uses it in pSeries_lpar_hpte_invalidate so we can tear down mappings with fewer hypervisor calls. Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07[POWERPC] Clear RI bit in MSR before restoring r13 when returning to userspacePaul Mackerras1-26/+33
Some instruction tracing tools use the RI (recoverable interrupt) bit in the MSR to indicate when it's safe to single-step. Currently we clear RI after restoring r13 when returning to userspace. However, if we single-step past the point where r13 is restored, we'll corrupt r13 in the exception entry code and not restore it. This moves the clearing of RI to just before r13 is restored so this doesn't happen. Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07[POWERPC] Fix performance monitor exceptionLivio Soares1-1/+1
To the issue: some point during 2.6.20 development, Paul Mackerras introduced the "lazy IRQ disabling" patch (very cool work, BTW). In that patch, the performance monitor unit exception was marked as "maskable", in the sense that if interrupts were soft-disabled, that exception could be ignored. This broke my PowerPC profiling code. The symptom that I see is that a varying number of interrupts (from 0 to $n$, typically closer to 0) get delivered, when, in reality, it should always be very close to $n$. The issue stems from the way masking is being done. Masking in this fashion seems to work well with the decrementer and external interrupts, because they are raised again until "really" handled. For the PMU, however, this does not apply (at least on my Xserver machine with a 970FX processor). If the PMU exception is not handled, it will _not_ be re-raised (at least on my machine). The documentation states that the PMXE bit in MMCR0 is set to 0 when the PMU exception is raised. However, software must re-set the bit to re-enable PMU exceptions. If the exception is ignored (as currently) not only is that interrupt lost, but because software does not re-set PMXE, the PMU registers are "frozen" forever. [This patch means that performance monitor exceptions are taken and handled even if irqs are off, as long as some other interrupt hasn't come along and caused interrupts to be hard-disabled. In this sense the PMU exception becomes like an NMI. The oprofile code for most powerpc processors does nothing that is unsafe in an NMI context, but the Cell oprofile code does a spin_lock_irqsave. However, that turns out to be OK because Cell doesn't actually use the performance monitor exception; performance monitor interrupts come in as a regular interrupt on Cell, so will be disabled when irqs are off. -- paulus.] Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07[POWERPC] Compile fixes for arch/powerpc dcr codeDavid Gibson5-2/+4
The new dcr code does not currently compile when configured for native DCR access on ARCH=powerpc. This patch fixes the problems. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-07[POWERPC] Maple: use mmio nvramNathan Lynch2-0/+4
Some systems supported by the maple platform (e.g. JS2x blades running SLOF) are able to use the mmio_nvram backend for reading and writing nvram. This is an improvement over the current situation -- no nvram access from userspace at all. Select MMIO_NVRAM for the maple platform. Initialize the mmio_nvram backend from maple setup code. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Paul Mackerras <paulus@samba.org>