| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-05-11 | riscv: add memory-type errata for T-Head | 4 | -1/+100 | |
| 2022-05-11 | riscv: implement module alternatives | 1 | -5/+9 | |
| 2022-05-11 | riscv: allow different stages with alternatives | 1 | -1/+2 | |
| 2022-05-11 | riscv: integrate alternatives better into the main architecture | 2 | -76/+0 | |
| 2022-01-09 | riscv: errata: alternative: mark vendor_patch_func __initdata | 1 | -1/+2 | |
| 2021-06-01 | riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled | 1 | -1/+1 | |
| 2021-04-26 | riscv: sifive: Apply errata "cip-1200" patch | 1 | -0/+18 | |
| 2021-04-26 | riscv: sifive: Apply errata "cip-453" patch | 3 | -0/+59 | |
| 2021-04-26 | riscv: sifive: Add SiFive alternative ports | 4 | -0/+75 | |
| 2021-04-26 | riscv: Introduce alternative mechanism to apply errata solution | 2 | -0/+70 |
